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VHDP Documentation

website·Indexed 32 days ago

https://vhdplus.com/

Documentation for VHDP, a language and IDE for FPGA design that translates to VHDL. It features structural syntax for components, generics, and packages, as well as process-oriented programming with Threads, Step functions, and sequential operations like Wait and SeqFor.

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What's inside VHDP

  1. Overview of VHDP language and timing control

    VHDP is a language based on VHDL designed for FPGAs. While it supports standard VHDL operations (If, Case, For), it introduces two specific constructs for managing execution cycles:

    1. Thread{}: Wraps code to allow the use of While and Wait statements, enabling code to run across multiple clock (CLK) cycles.
    2. Step{}: Wraps operations that must be executed exactly one clock cycle later than the preceding operations (e.g., to sequence a signal high then low).

  2. Overview of the Camera and Display extension

    The Camera and Display extension is used for programming object detection, creating safety cameras, and other video-based applications. It supports high-speed data transfer via differential pairs to enable HD video capture and display with high frame rates. Supported hardware interfaces include state-of-the-art CSI cameras (such as the Raspberry Pi Camera) and standard HDMI. The extension utilizes the CRUVI HS connector.

  3. Introduction to the VHDP Programming Language

    VHDP is a superset of VHDL designed to reduce code volume (up to 95% reduction) while maintaining 100% FPGA performance. It simplifies FPGA development by automatically creating state machines and providing synthesizable loops, delays, and functions. Because it is a superset, it remains fully compatible with classic HDLs, allowing developers to mix different languages within the IDE.

  4. Overview of the MAX10 Shield for Core MAX10

    The MAX10 Shield is an expansion board for the Core MAX10 FPGA. It expands connectivity by adding three CRUVI connectors and three PMOD interfaces, allowing for the simultaneous connection of cameras, motors, and ultrasonic sensors. It is designed to allow the FPGA to be powered using the same supply as the motors.

  5. Overview of VHDPlus IDE features

    VHDPlus IDE is a modern development environment designed to make FPGA programming more accessible. Key features include:

    • Language Support: Supports VHDP, VHDL, Verilog, and other HDL languages.
    • Code Assistance: Provides code suggestions, autocorrection, and error listing.
    • Simulation: Includes a simulation assistant to verify programs and fix mistakes before the time-consuming HDL synthesis process.
    • Quartus Integration: Built-in integration with Intel Quartus for pin connection, compilation, and programming. Available on Windows and Linux.
    • Software Support: First-class C++ support and a debugger for programming NIOS II Softcore processors.

  6. Overview of Core MAX10 FPGA Board

    The Core MAX10 is an entry-level FPGA programming board. It features numerous I/Os, an internal ADC, large RAM, Flash, and an onboard USB programmer. It includes an internal Arduino-compatible processor, allowing for complex projects with multiple integrated components.

  7. Overview of the IAS Camera and Display extension

    The IAS Camera and Display extension connects OnSemi cameras (using the IAS connector) to an FPGA development board via a CRUVI HS connector. It includes an onboard power supply and oscillator, simplifying the setup to just the extension, FPGA board, and camera. The hardware supports 4 MIPI CSI-2 lanes for camera input and features a standard HDMI port for image output, making it suitable for applications like object detection and safety cameras.

  8. Define and use Signals in VHDP

    Signals act as variables shared across one or more processes or NewComponent. They are globally readable within the file but can only be written to by a single process.

    Key Behavior:

    • Update Cycle: Assignments to signals take effect in the next cycle. To update a value instantly, use a Variable instead.
    • Scope: Signals can be declared anywhere signals are assignable or within a dedicated AttributeDeclaration{} section.

  9. Use the built-in Serial Monitor in VHDPlus IDE

    Starting with version 0.9.2.9, the VHDPlus IDE includes a built-in Serial Monitor. This tool allows developers to establish direct communication with their connected hardware for debugging and data exchange.

  10. View signal types and documentation via Hover

    To determine the type of a signal or retrieve information about a specific part of the code, hover the mouse cursor over the name of the element. This action displays the type information and any associated comments provided next to the signal declaration.

  11. Use ModelSim for VHDL simulation and debugging

    ModelSim is required to simulate VHDL programs. Simulation allows developers to set inputs for the Main entity or specific Components to trigger operations and observe signal changes over time. This process helps identify errors and verify code behavior without the need to program the FPGA hardware for every iteration.

  12. Understand VHDPlus Audio Extension hardware capabilities

    The Audio extension is designed for analog audio data reception and output, enabling the creation of audio mixers, synthesizers, or voice recognition systems using FPGA processing. It is powered by a MAX9867 Audio Codec featuring two 18-bit, 48kHz ADCs and DACs.