DOCSEARCHbyAlgolia
Submit Docs

AMD Vivado Design Tutorials

repository·2025.2·Indexed 42 days ago

https://github.com/xilinx/vivado-design-tutorials

In-depth tutorials for the AMD Vivado design environment, covering design methodologies and programming models for FPGA and Adaptive SoC architectures. Includes specialized guidance on Versal reset distribution architectures, Dynamic Function eXchange (DFX) flows, embedded IOBs in reconfigurable partitions, and the use of Block Design Containers (BDC) in IP Integrator.

Tokens
169.6K
Snippets
289
Records
744
Agent score
54%

What's inside Vivado Design Tutorials

  1. Overview of the 2D Eye Scan Tutorial

    2025.2
    This tutorial demonstrates how to use the 2D Eye Scan function on the integrated Versal™ Adaptive SoC DDR Memory Controller (DDRMC). The 2D Eye Scan provides a graphical representation of the data margin available by adjusting the Vref for either read or write operations. This is used to characterize the signal integrity of the memory interface.

  2. Overview of Segmented Configuration for AMD Versal devices

    2025.2

    Segmented Configuration in Vivado 2025.2 allows for splitting programming images to incrementally configure device sections. This enables faster booting of processors and memory to load an operating system by deferring Programmable Logic (PL) configuration.

    Key benefits include:

    • Quickly booting processors and memory for OS loading.
    • Deferring PL configuration.
    • Enabling PL image delivery over secondary boot interfaces (e.g., PCIe via CPM/QDMA or Gigabit Ethernet).
    • Enabling dynamic reloading of the entire PL configuration.

    Note: This feature is a production release in Vivado 2025.2. For first-generation Versal devices, it is optional and off by default. For second-generation Versal devices (e.g., Versal AI Edge Gen 2, Versal Prime Gen 2), it is always enabled and cannot be disabled.

  3. Overview of VCK190 eMMC Bring Up Tutorial

    2025.2

    This tutorial provides instructions for the first-time usage or recovery of an eMMC flash on the VCK190 Versal Adaptive SoC evaluation board. Because the eMMC boot module connects to PMC MIO 0~11 via the FMC slot, the QSPI must be disabled, and the SD1 controller must be used.

    There are two primary workflows:

    1. Without Vivado HW Manager: Requires creating two separate Vivado projects (one for SD boot and one for eMMC boot).
    2. With Vivado HW Manager: Uses a specific design optimized for eMMC.

    Objectives:

    • Format and partition the eMMC flash properly.
    • Recover a corrupted eMMC flash that fails to boot to Linux.

  4. Overview of Performance AXI Traffic Generator

    2025.2

    The Performance AXI Traffic Generator is used to model traffic masters in Versal™ Adaptive SoC designs to evaluate the performance of Network on Chip (NoC) based solutions. It supports AXI3, AXI4, and AXI4-Stream protocols and offers high configuration flexibility for dynamic workloads.

    There are two primary versions of the IP:

    1. Non-Synthesizable: For simulation use cases only.
    2. Synthesizable: For both simulation and hardware execution.

    Detailed IP documentation can be found in PG381.

  5. Overview of Versal NoC and DCMAC Connectivity

    2025.2

    This tutorial demonstrates how to use the AMD Versal™ programmable Network on Chip (NoC) to transport high-bandwidth data between hard IP blocks, specifically focusing on the DCMAC (600G Channelized Multirate Ethernet Subsystem).

    Key concepts:

    • Versal NoC: An AXI-interconnecting network used for data sharing between Programmable Logic (PL), Processing System (PS), and other hard blocks.
    • DCMAC: A hard IP supporting Ethernet links with up to 600 Gb/s combined bandwidth.
    • Segmented AXI-Stream (AXI-S): The DCMAC uses segmented AXI-S interfaces (multiple 128-bit wide segments) to maintain high bandwidth and minimize idle bytes during unaligned transfers. This is a common interface for high-speed Ethernet IPs like HSC or MRMAC.

    The primary advantage of using the NoC for these interfaces is that it allows transporting high-speed data (e.g., 400 Gb/s Ethernet) between distant hard IP blocks, such as those in different Super Logic Regions (SLR), without consuming significant fabric resources or facing the timing closure and routing challenges of wide high-speed buses.

  6. Overview of the Versal Schematic Checker Tool

    2025.2

    The Versal™ Schematic Checker is a tool designed to automate parts of the Versal Adaptive SOC Schematic Review Checklist (XTP546). It operates as a separate tab within the checklist environment, allowing users to validate netlists against hardware requirements.

    Supported Netlist Formats:

    • Cadence OrCAD (pstchip.dat, pstxnet.dat, and pstxprt.dat)
    • Cadence Allegro (.tel)
    • Cadence Concise
    • Mentor Graphics Pads (.asc)
    • Pads Logic
    • Altium ORCAD2PCB
    • Intel Schematic Connectivity Format (.iscf)

    Key Capabilities:

    • Validates pin counts and power/ground pin matches.
    • Checks voltage values against datasheet specifications.
    • Verifies signal terminations (e.g., GTY RREF, IO_VR, and memory interfaces).
    • Performs signal polarity checks (P/N swaps).
    • Validates MIO and Memory pin connections based on user-defined interfaces.

  7. Overview of Dynamic Function eXchange (DFX) Tutorials

    2025.2

    This collection provides tutorials that augment the fundamental concepts found in the Dynamic Function eXchange Tutorial Guide (UG947). These tutorials focus on design flow features that are common to all devices supporting DFX, rather than being specific to a single architecture.

    If you require device-specific DFX guidance, refer to the following categories:

    • UltraScale+
    • Versal

  8. Overview of Multi-Bank Source Synchronous Design

    2025.2

    This tutorial demonstrates a multi-bank configuration for Versal™ Adaptive SoC XPHY I/O source synchronous interfaces using the Advanced I/O Wizard (AIOW).

    Key Characteristics:

    • Bank Configuration: Supports up to three banks. This specific design uses two adjacent banks. One bank provides three XPHY NIBBLESLICEs and the other provides two XPHY NIBBLESLICEs for data transmission and reception.
    • Clocking: The transmit clock is forwarded via clock forward pins. Each bank has its own transmit clock and its own receiver capture clock.
    • Standard: Uses the LVDS standard for I/Os (differential I/O pin pairs for data, transmit/capture clock, and PLL input clock).
    • Hardware Requirements: Designed for the VCK190 board using the FMC XM107 loopback card. It utilizes the onboard SI570 Clock2 as a clock source.
    • Verification: Uses a PRBS (Pseudo-Random Binary Sequence) generator and checker to validate data integrity via an external loopback.

  9. Introduction to Versal NoC Data Movement Tutorial

    2025.2

    This tutorial demonstrates how the Versal™ Network on Chip (NoC) simplifies on-chip data movement compared to Zynq™ UltraScale+™ designs. It uses a k-means clustering acceleration design to compare resource utilization and performance. The primary advantage highlighted is that the Versal NoC frees up programmable logic (PL) resources that would otherwise be consumed by SmartConnect in an UltraScale+ design.

    Key Comparison Points:

    • Versal: Uses NoC for data movement between PL and DDR memory.
    • UltraScale+: Uses SmartConnect for similar data movement, consuming more PL resources.

    Tutorial Structure:

    1. Design Description
    2. k-Means Kernel Description
    3. Building and Running on Versal Adaptive SoCs
    4. Building and Running on UltraScale+ Devices
    5. Comparison of Results

  10. Overview of Versal HBM Performance Tuning: Address Mapping

    2025.2

    This module investigates how different traffic patterns and address mappings impact the performance of the High Bandwidth Memory (HBM) subsystem in Versal devices.

    Users will perform the following tasks:

    1. Evaluate Linear Access Patterns: Test performance using a linear access pattern with the default HBM controller address mapping.
    2. Evaluate Random Access Patterns: Compare results by switching to random accesses while maintaining the default address mapping.
    3. Analyze Bottlenecks: Identify how DRAM bottlenecks affect performance.
    4. Optimize via Address Mapping: Explore and verify alternative address mappings to improve performance through simulation.

    Prerequisites:

  11. Overview of Versal OSPI Boot Tutorial

    2025.2

    This tutorial demonstrates the Octal SPI (OSPI) primary boot mode flow in single mode for Versal Adaptive SoCs, specifically targeting the VCK190 evaluation board.

    Key concepts include:

    • OSPI Boot Mode: Supports an 8-bit data bus width. The BootROM executes in Single Data Rate (SDR) mode, while the Platform Loader and Manager (PLM) switches the OSPI to Double Data Rate (DDR) mode.
    • Platform Management Controller (PMC): Manages the boot and lifecycle. It includes the ROM Code Unit (RCU) for initial boot setup and the Platform Processing Unit (PPU) for loading the platform.
    • Programmable Device Image (PDI): The boot image used to program and configure the Versal device.
    • CIPS (Control Interfaces and Processing System): Configures PMC/PS peripherals, clocks, and MIO.

  12. Overview of Versal Boot and Configuration Tutorials

    2025.2

    This collection of tutorials covers various methods for booting and configuring Versal Adaptive SoC devices. It is organized into three main areas:

    1. Segmented Configuration: Explains the Segmented Configuration boot solution. This includes the Vivado tool flow, current limitations, and methods for delivering the PL (Programmable Logic) programming image via PetaLinux or U-Boot.
    2. VCK190 Boot Mode Tutorials: Focuses on first-generation Versal devices, specifically designed for use with the VCK190 evaluation platform.
    3. Versal Gen 2 Boot Mode Tutorials: Focuses on second-generation Versal devices and their specific boot modes and utilities.