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Vitis Accelerated Libraries

repository·main·Indexed 22 days ago

https://github.com/xilinx/vitis_libraries

A suite of high-performance, open-source libraries for AMD Vitis platforms providing hardware acceleration for math, DSP, vision, and domain-specific workloads. The libraries are organized into three tiers: L1 (HLS Flow) for individual kernel functionality, L2 (Kernel/Device Flow) for building XCLBIN files, and L3 (Application Flow) for high-level software APIs. Supported platforms include Alveo U280, U50, U250, and U200, requiring Vitis 2022.2 or later and Xilinx Runtime (XRT).

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What's inside Vitis Libraries

  1. Overview of the ISP all_in_one Pipeline

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    The ISP all_in_one pipeline is a comprehensive image sensor processing pipeline that allows users to test various combinations of image processing modules. Modules can be enabled or disabled at compile-time using specific flags. The pipeline includes 19 modules covering tasks from exposure extraction and HDR merging to color space conversion.

  2. Overview of Ultrasound Library Level 2 (L2) APIs

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    The Level 2 (L2) of the Vitis Ultrasound Library provides host-callable kernels implemented as AIE graphs. These kernels are built upon L1 kernels and provide the mathematical components necessary for the beamformation of RF (radio frequency) data. The L2 APIs allow developers to perform complex ultrasound processing tasks such as image point generation, delay computation, focusing, apodization, and interpolation.

  3. Introduction to AIE Solver Library

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    The AIE Solver library provides a set of linear-algebra library elements optimized for the AI Engine (AIE). Each library element is structured into several components:

    • Main Graph Class: Used to integrate the library element as a subgraph within your design.
    • Kernel Classes: The underlying computational kernels.
    • Reference Models: Graph and kernel classes used for verification and modeling.

    Developers typically use these elements to implement complex linear algebra operations (like Cholesky, QRD, SVD, or Substitution) within an AI Engine graph.

  5. Overview of the Vitis Motor Control Library APIs

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    The Vitis Motor Control Library is a C/C++ library designed to accelerate motor control application development. It provides two tiers of APIs:

    Algorithm-level L1 APIs

    These are the primary functional blocks for motor control:

    • FOC: Sensor-based Field-Oriented Control. Supports eight control modes including basic speed control, torque control, and field-weakening control. Includes an AXI-Lite interface for system control and monitoring.
    • SVPWM_DUTY: The front-end for Space Vector Pulse Width Modulation (SVPWM) used to calculate duty ratios. Includes an AXI-Lite interface.
    • PWM_GEN: The back-end for SVPWM that generates output signals based on the calculated ratios. Includes an AXI-Lite interface.
    • QEI: Quadrature Encoder Interface for reading encoder signals. Includes an AXI-Lite interface.

    Operator-level APIs

    Lower-level mathematical operators used within the control loops, including:

    • Clarke transform and its inverse transform
    • Park transform and its inverse transform
    • PID controllers

    Note: The library utilizes ap_fixed data types to balance precision and ease of development. For verification, a virtual motor model is available to test the eight FOC modes within the AMD Vitis environment.

  6. Overview of the ISP Multistream Pipeline

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    The ISP (Image Signal Processor) multistream pipeline enables the processing of multiple input streams using a single instance of the ISP.

    Key Characteristics:

    • Stream Processing: Currently processes four streams using a Round-Robin method.
    • Input Type: XF_16UC1 (16-bit unsigned, single channel).
    • Output Type: XF_8UC3(RGB) (8-bit unsigned, 3-channel RGB). After color conversion to the YUV color space, the final output type is XF_16UC1(YUYV).
    • Pipeline Stages: The pipeline consists of nine functional blocks:
      1. Extract Exposure Frames: Extracts Short and Long Exposure frames using the Digital overlap parameter.
      2. HDR Merge: Generates High Dynamic Range images from different exposure frames.
      3. Black Level Correction: Corrects black and white levels to prevent whitening in dark regions and improve contrast.
      4. Gain Control: Improves overall image brightness.
      5. Demosaicing: Reconstructs RGB pixels from Bayer patterns (RGGB, BGGR, RGBG, GRGB).
      6. Auto White Balance (AWB): Improves color balance using image statistics.
      7. Color Correction Matrix (CCM): Converts input color format to output format using a user-provided matrix (CCM_TYPE).
      8. Local Tone Mapping: Enhances contrast and brightness by considering pixel neighbor statistics.
      9. Gamma Correction: Improves overall brightness.
      10. Color Space Conversion: Converts RGB to YUV422 (YUYV) for HDMI display compatibility.

  7. Overview of the ISP all_in_one_adas Pipeline

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    The ISP all_in_one_adas pipeline is a comprehensive image sensor processing suite designed to test various combinations of image processing modules. It is suitable for applications like Surround View Systems (SVS), INCABIN, and Forward/Rear view pipelines.

    Key capabilities include:

    • HDR Processing: Accepts interleaved Short Exposure Frames (SEF) and Long Exposure Frames (LEF) to generate High Dynamic Range (HDR) merged output.
    • Image Correction: Includes Bad Pixel Correction (BPC), Black Level Correction, and Gain Control.
    • Color & Pattern Conversion: Supports RGBIR to Bayer conversion, Demosaicing (RGGB, BGGR, RGBG, GRGB), Auto White Balance (AWB), and Color Space Conversion (e.g., RGB to YUV422/YUYV).
    • Tone Mapping & Gamma: Provides Global Tone Mapping (GTM), Local Tone Mapping (LTM), and Gamma Correction.
    • Advanced Color Manipulation: Supports Color Correction Matrix (CCM) and 3D LUT operations.

  9. Overview of QRD (QR Decomposition) Kernel

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    The QRD kernel performs QR decomposition, which decomposes a matrix $A$ into an orthogonal matrix $Q$ and an upper triangular matrix $R$ ($A = QR$). This specific implementation uses the Gram-Schmidt process and is optimized for Versal devices.

    Key characteristics:

    • High Performance: Can achieve 790+ GFLOPS for a complex float 1024*256 matrix on VCK190.
    • Scalability: Resource usage and performance scale linearly with matrix dimensions (e.g., a 25664 matrix uses proportionally fewer resources than a 1024256 matrix).
    • Use Cases: Solving linear least squares problems and implementing the QR algorithm for eigenvalues.

  10. Overview of the Vitis Motor Control Library

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    The Vitis Motor Control Library is a C/C++ library designed to accelerate the development of motor control applications. It provides four primary algorithm-level L1 APIs that include AXI configuration interfaces. These APIs can be integrated into larger systems using the IPI (Intellectual Property Integration) flow.

    Core L1 APIs:

    • FOC: Implements sensor-based Field-Oriented Control, supporting speed control, torque control, and field-weakening modes.
    • SVPWM_DUTY: Acts as the front-end for Space Vector Pulse Width Modulation (SVPWM) to calculate duty cycle ratios.
    • PWM_GEN: Acts as the back-end for SVPWM to generate actual output signals based on the calculated ratios.
    • QEI: Implements the Quadrature Encoder Interface (QEI) for position/speed sensing.

  12. Overview of Vitis Accelerated Libraries

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    Vitis Accelerated Libraries are a collection of open-source, performance-optimized libraries designed for the AMD Vitis™ Unified Software Platform. They provide out-of-the-box acceleration for various workloads with minimal code changes.

    Key features include:

    • Core Functionality: Common libraries for Math, Linear Algebra, and DSP.
    • Domain-Specific Acceleration: Specialized libraries for Vision and Image Processing, Security, Ultrasound, Motor Control, and more.
    • Multi-Language Support: APIs are available for C, C++, Python, and Matlab.
    • Scalability: Libraries can be deployed across AMD platforms at the edge, on-premise, or in the cloud.
    • Flexible Usage: Use them as plug-and-play APIs for rapid prototyping, or use library functions as algorithmic building blocks to design custom accelerators.