Vitis Data Center Acceleration Examples

This example demonstrates vector addition using the XRT (Xilinx Runtime) Native APIs. It is designed to illustrate how to interact with hardware devices, manage memory buffers, and execute kernels using C++.

Key Concepts:

• XRT Native APIs: The low-level interface for managing kernels and hardware resources.
• Task Level Parallelism: The kernel utilizes HLS Dataflow to schedule multiple tasks together for higher throughput.

Note: This example is not compatible with NoDMA platforms (e.g., u50 nodma).

This example uses XRT Native APIs to measure host memory and kernel bandwidth. It utilizes three distinct kernels:

1. read_bandwidth: Measures read throughput.
2. write_bandwidth: Measures write throughput.
3. bandwidth: Measures concurrent read and write throughput.

The host application executes these kernels with varying buffer sizes and reports the maximum bandwidth achieved for each operation type (Read, Write, and Concurrent).

The Host Memory Bandwidth application is designed to measure the throughput of host memory access. It utilizes three distinct kernels:

1. read_bandwidth: Measures read throughput.
2. write_bandwidth: Measures write throughput.
3. bandwidth: Measures concurrent read and write throughput.

The application iterates through various buffer sizes and reports the throughput (in GB/sec) for each kernel, ultimately identifying the maximum bandwidth achieved for each operation type.

The AXI Burst Performance design is a benchmarking tool used to measure the time required to write a buffer into DDR or read a buffer from DDR. It is designed to evaluate how different hardware parameters impact effective throughput.

The design includes two sets of 6 kernels. Each set uses a different data width, and within each set, individual kernels are configured with varying burst_length and num_outstanding parameters to allow for comparative performance analysis.

This example demonstrates an RTL-based acceleration workflow where two simple increment RTL kernels are connected via a stream interface. To facilitate host communication, the kernels are connected to the host using memory-mapped C++ data mover kernels (krnl_mm2s and krnl_s2mm).

Key Concepts:

• RTL Kernel: Custom hardware logic integrated into the Vitis acceleration flow.
• Read/Write Stream: Data transfer mechanism using streaming interfaces.
• Keywords: ap_axiu (AXI4-Stream interface) and hls::stream (HLS stream library).

Excluded Platforms:

• All Versal Platforms (e.g., vck190)
• ZC706 Evaluation board
• All NoDMA Platforms (e.g., u50 nodma)
• Versal V70

This repository provides reference implementations for developing accelerator applications on AMD Alveo Data Center platforms. It focuses on specific scenarios involving host code and kernel programming.

Prerequisites: Users should have a basic understanding of the Vitis programming model and should have completed the Vitis HLS Introductory Examples and Vitis Tutorials before using these examples.

This application measures host memory bandwidth by running three distinct kernels with variable buffer sizes:

1. read_bandwidth: Measures read throughput.
2. write_bandwidth: Measures write throughput.
3. bandwidth: Measures concurrent read and write throughput.

The application reports the throughput in GB/sec for each buffer size and identifies the maximum bandwidth achieved for each operation type.

The project is organized into source code and compiled binary directories:

• src/: Contains the application C++ source code (e.g., host.cpp, kernel implementations).
• xclbin/: This directory is required by the Makefile; it will be populated with the compiled .xclbin files during the build process.