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AMD Vitis Unified Software Platform Tutorials

repository·2026.1·Indexed 23 days ago

https://github.com/xilinx/vitis-tutorials

In-depth tutorials for the AMD Vitis™ Unified Software Platform, covering FPGA fabric, Arm® processor subsystems, and AI Engines. Includes detailed guides on AI Engine-ML programming, matrix multiplication optimization, and implementing a Prime Factor FFT-1008 on the VE2802 device. Covers environment setup for Vitis 2026.1, AIE-ML simulation and emulation workflows, and performance analysis using Vitis Analyzer.

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What's inside xilinx-vitis-tutorials

  1. Overview of the AMD Versal AI Engine LeNet Tutorial

    2026.1
    This tutorial demonstrates how to implement the LeNet algorithm for image classification using a heterogeneous system design on AMD Versal™ adaptive SoCs. The design partitions tasks between the AI Engine (for matrix multiplication and fully connected layers) and the Programmable Logic (PL) (for input pre-processing, max pooling, and data rearrangement). It covers the complete Vitis™ unified software platform flow, including AI Engine Adaptive Data Flow (ADF) API graph creation, PL kernel compilation, and system integration using the Vitis compiler (V++).

  2. Overview of the Polyphase Channelizer Design

    2026.1
    The Polyphase Channelizer tutorial implements a high-speed design that simultaneously downconverts frequency-division multiplexed (FDM) channels from a single data stream. This implementation utilizes a combination of AI Engine and programmable logic (PL) resources on AMD Versal™ adaptive SoC devices to handle high sampling rates (up to 10.5 GSPS).

  3. Overview of Versal 2D-FFT Implementation Tutorial (XD073)

    2026.1

    This tutorial (XD073) compares two different implementation methodologies for a 2D-FFT algorithm on AMD Versal™ adaptive SoCs:

    1. AI Engine Implementation: Uses the AI Engine Adaptive Data Flow API (ADF) graph.
    2. HLS Implementation: Uses AMD Vitis™ HLS targeting Programmable Logic (PL) and DSP Engines.

    The tutorial covers hardware emulation (hw_emu) and full hardware (hw) flows. It allows users to compare performance, throughput, power, and utilization across different matrix dimensions and kernel instance counts.

  4. Overview of Versal Custom Platform Integration using Vitis Subsystem

    2026.1

    This tutorial demonstrates how to design, verify, and deploy an AI Engine (AIE) and HLS-based DSP subsystem on a custom Versal platform using AMD 2026.1 tools.

    Key workflow components include:

    • Vitis Subsystem (VSS) Development: Creating components targeting a specific device part number to allow independent development from the platform.
    • Vitis Export to Vivado Flow: Finalizing designs in Vivado with full control over synthesis and implementation before exporting a fixed XSA.
    • Hardware/Software Integration: Integrating VSS components into extensible Vivado platforms and building embedded Linux environments (via Yocto/EDF or PetaLinux) to run host applications.

  5. Overview of the Fractional Delay Farrow Filter Tutorial

    2026.1

    This tutorial demonstrates how to implement a Fractional Delay Farrow Filter using AMD Vitis AI Engine APIs. A Farrow filter is a digital signal processing (DSP) algorithm used for timing synchronization in applications like digital receivers.

    Key characteristics of the Farrow structure used in this tutorial:

    • Real-time tuning: The fractional delay can be adjusted in real-time without reloading coefficients, as the polynomial coefficients remain constant.
    • Efficiency: It utilizes Horner's rule to evaluate polynomials of degree $P$ using only $P$ multiplications and $P$ additions.
    • Implementation Goal: The tutorial starts with a functionally accurate model and progresses through code optimizations to meet specific throughput targets.

    Target Specifications:

    • Sampling Rate: 1 Gsps
    • I/O Data Type: cint16
    • Coefficients Data Type: int16
    • Delay Input Data Type: int16

  6. Overview of Versal GeMM Implementation Tutorial

    2026.1

    This tutorial provides two different implementations of a General Matrix Multiplication (GeMM) system-level design on Versal™ adaptive SoCs to compare performance and methodology:

    1. AI Engine (AIE) Implementation: Uses a 24-AIE core overlay to multiply square matrices. It divides matrices into specific blocks (e.g., MatA into 3x8 and MatB into 8x3) and uses input/output streams to maintain high performance across various matrix dimensions (from 32x32x32 up to 1024x1024x1024).
    2. DSP Implementation: Uses a systolic array of 1024 DSP58 Engines. It decomposes matrix-matrix multiplication into matrix-vector multiplication using 32 DSP58 cascade chains. The design breaks larger matrices into 32x32 submatrices.

    The tutorial covers the complete Vitis software flow, including ADF graph creation, host application and PL kernel compilation, linking with the Vitis compiler (V++), packaging, and running through hardware emulation (hw_emu) and hardware (hw) flows.

  7. Overview of the N-Body Simulator tutorial modules

    2026.1

    The tutorial is structured into seven sequential modules that progress from software simulation to full hardware implementation:

    • Module 01 - Python Simulations on x86: Python implementation and x86 execution timing.
    • Module 02 - AI Engine Design: Implementation of the AI Engine kernels (nbody()), subsystems, and the full 400-tile system.
    • Module 03 - PL Kernels: Creation of PL HLS datamover kernels and packet switching kernels.
    • Module 04 - Full System Design: Linking AI Engine and PL kernels into a single XCLBIN.
    • Module 05 - Host Software: Host applications for data validation, performance profiling (A72 vs AI Engine), and animation data generation.
    • Module 06 - SD Card and Hardware Run: Creating sd_card.img and executing the design on hardware.
    • Module 07 - Results: Performance analysis, GFLOPS estimation, and bandwidth exploration.

    Note on Design Scales: While the tutorial builds the 100 Compute Unit design (using all 400 tiles), intermediate designs (x1_design and x10_design) are provided for faster build times and hardware emulation.

  8. Introduction to Polyphase Channelizer on AIE-ML

    2026.1

    This tutorial demonstrates how to build high-performance polyphase channelizers using AMD Vitis™ Libraries on AIE-ML and programmable logic (PL) in AMD Versal™ adaptive SoC devices. A polyphase channelizer simultaneously down-converts frequency-division multiplexed (FDM) channels from a single data stream.

    Key IP elements used from the Vitis Libraries include:

    • TDM FIR: Used for time-division multiplexed FIR filtering.
    • 2D FFT/IFFT Vitis subsystem: Used for efficient 2D FFT/IFFT operations.

    For large point sizes and SSR > 1 regimes, implementing a 1D IFFT using a 2D IFFT algorithm is more efficient but requires resources spanning both AIE and PL.

  9. Overview of the Packet Sender (packet_sender) kernel

    2026.1

    The packet_sender is a high-performance AMD Vitis HLS kernel designed for TDM (Time-Division Multiplexing) FIR packet switching systems. It converts continuous streams of complex samples into packetized AXI-Stream outputs formatted for AMD AI Engine consumption.

    Key Specifications:

    • Throughput: 1.25 Gsps per stream (2.5 Gsps total for dual streams) at 312.5 MHz.
    • Data Width: 128-bit AXI-Stream.
    • Architecture: Dataflow architecture using a Consumer-Producer model with hls::stream_of_blocks for synchronization.
    • Resource Efficiency: Uses LUTRAM-based buffering, resulting in zero BRAM utilization.

  10. Overview of the Versal AI Engine-ML LeNet Tutorial

    2026.1

    This tutorial demonstrates how to implement the LeNet algorithm for image classification using the AMD Versal adaptive SoC AI Engine-Machine Learning (AIE-ML) architecture. The design showcases functional partitioning between the AI Engine-ML and Programmable Logic (PL), memory hierarchy management (DDR, PL block RAM, and AIE-ML memory), and the use of the AXI4-Stream interface.

    Key objectives include:

    • Building a complete system design using the AMD Vitis unified software platform flow.
    • Mapping CNN layers (convolutional and fully connected) to AIE-ML and PL compute blocks.
    • Implementing kernels for matrix multiplication in AIE-ML and data rearrangement/max pooling in PL.
    • Using graph control APIs for runtime updates via the Runtime Parameter (RTP) interface.
    • Running the design through hardware emulation and hardware flows.

  11. Overview of the RTL Counter IP

    2026.1

    The RTL Counter is a packaged RTL kernel (in .xo format) designed to be integrated into a Vitis system. Its primary functions are:

    1. Kernel Packaging: Demonstrates how to use Vivado to create a packaged RTL kernel for Vitis integration.
    2. Data Stimuli: Generates input data to measure propagation delay in clock cycles for dataflow signal processing paths in the AI Engine (AIE).

    Technical Specifications:

    • Output: Generates 5 copies of AXI Stream data.
    • Data Format: Sends two samples of cint16 per clock cycle.
    • Width: Designed to match the native 64-bit AIE PLIO port width.
    • Clock Speed: Can be clocked up to 625 MHz.
    • Backpressure Behavior: The counter is a freerunning counter that disregards tready backpressure from receiving blocks. This allows users to identify backpressure occurrences by detecting gaps in the counter sequence for specific data paths.

  12. Overview of Prime Factor FFT-1008 on AIE-ML

    2026.1

    This tutorial demonstrates how to implement a Prime Factor Algorithm (PFA) 1008-point Fast Fourier Transform (FFT) on the AIE-ML architecture (specifically for the VE2802 device).

    Key Concepts

    • Algorithm: The PFA approach decomposes a DFT of size $N = N_1 imes N_2$ into two-dimensional DFTs of sizes $N_1$ and $N_2$, provided they are relatively prime.
    • AIE-ML Advantage: AI Engines compute small-dimension DFTs ($N < 32$) efficiently using direct vector/matrix multiplication. This tutorial maps short-length DFT-7, DFT-9, and DFT-16 transforms to the AI Engines.
    • Architecture Mapping:
      • DFT Kernels: Mapped to AI Engines using vector-matrix DFTs.
      • Memory Transpose: Unlike previous AIE architectures that used Programmable Logic (PL) for transposes, this design maps intermediate memory transpose operations to Memory Tiles within the AIE-ML array to simplify data flow.
      • Permutations: Input and output permutation blocks are implemented in the PL using RTL generated via AMD Vitis™ High Level Synthesis (HLS) from untimed C++ models. These remain in the PL because they require modulo addressing not supported by Memory Tile buffer descriptors (BDs).