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Vitis HLS Introductory Examples

repository·master·Indexed 21 days ago

https://github.com/xilinx/vitis-hls-introductory-examples

A repository of C/C++ synthesizable examples for AMD Vitis HLS. The collection covers DSP, memory partitioning, task-level parallelism, interface protocols (AXI Master, AXI Lite, AXI Stream), and pipelining. It includes demonstrations of the LogiCORE FFT, cache interface pragmas, and array stencils, providing automation via Python and Tcl scripts for C simulation, synthesis, and co-simulation within the Vitis Unified IDE.

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What's inside vitis-hls-introductory-examples

  1. Overview of Vitis HLS Introductory Examples

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    This repository provides a collection of C/C++ synthesizable examples designed to demonstrate various High-Level Synthesis (HLS) concepts. Each example includes C/C++ source code, a testbench, a README, and automation scripts (Tcl or Python) or configuration files.

    Examples are categorized by technical focus:

    • DSP: Demonstrates DSP Intrinsic Library and Vivado LogiCore FFT and FIR usage.
    • Array: Shows memory array partitioning techniques (e.g., complete, block cyclic).
    • Interface: Covers interface protocols such as AXI Master, AXI Lite, and AXI Stream.
    • Modeling: Focuses on loop essentials, arbitrary precision types, vectors, and conditional pragma control.
    • Pipelining: Illustrates fundamental HLS pipelining concepts.
    • Task_Level_Parallelism: Demonstrates Dataflow and free-running streams using hls::task.
    • Misc: Includes specialized flows like RTL blackbox.
    • Migration: Provides scripts (Tcl, Python, and CLI) for migrating to the Vitis Unified IDE.

  2. Understand the FFT design variations

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    These examples demonstrate different ways to instantiate the AMD/Xilinx LogiCORE FFT. The variations depend on the top-level interface (array vs. stream), data type (fixed-point vs. floating-point), and Super Sample Rate (SSR).

    Design nameTop level interfacesFFT lengthData typesSuper sample rate
    comp_interface_arrayarray102416-bit (fixed point)no
    comp_interface_streamstream102416-bit (fixed point)no
    comp_interface_array_float_ssr2array102432-bit (floating-point)2
    comp_interface_stream_float_ssr2stream102432-bit (floating-point)2
    logicore_fft_float_ssrarray or stream102432-bit (floating-point)2

    Key Concepts:

    • Interface Modes: The FFT C++ instantiation supports both array and hls::stream<> access modes for the input (xn) and output (xk) variables.
    • Super Sample Rate (SSR): SSR2 implementations trade increased area (more LUTs, FFs, BRAMs, and DSPs) for approximately 2x throughput improvement.

  3. Files included in the Direct I/O stream example

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    This package contains the following files for implementing and testing the Direct I/O stream example:

    • dut.cpp: Design Under Test implementation.
    • dut.h: Header file for the Design Under Test.
    • tb.cpp: Testbench implementation.
    • run_hls.tcl: TCL script for HLS synthesis.
    • run.py: Python script for design execution.
    • config.cfg: Configuration file.
    • README: Documentation file.

  5. Files included in the 2D Array Stencil package

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    The following files are part of the using_array_stencil_2d example package:

    • filter2d_hw.cpp: Hardware implementation of the 2D filter.
    • filter2d_sw.cpp: Software implementation of the 2D filter (used for verification).
    • cmdlineparser.cpp / cmdlineparser.h: Command line argument parsing utilities.
    • coefficients.h: Header defining filter coefficients.
    • common.h: Common definitions and headers.
    • hls_testbench.cpp: The HLS testbench used to verify the hardware implementation.
    • run_hls.tcl: Tcl script for running HLS synthesis.
    • README: Package documentation.

  6. Use HLS cache to improve performance when bursting fails

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    This example demonstrates how to use the #pragma HLS cache directive to manage data locality when Vitis HLS is unable to perform burst transfers on a specific interface. By using the cache pragma, you can specify how many lines of data should be cached and the depth of the cache to optimize memory access patterns.

    #pragma HLS cache port=in lines=16 depth=512

  7. Use the HLS cache interface pragma

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    This example demonstrates the use of the cache interface pragma to manage burst failures. The pragma allows you to specify the number of lines and the depth for a specific port.

    In this specific design, the following pragma is applied to the input port: #pragma HLS cache port=in lines=8 depth=128

    #pragma HLS cache port=in lines=8 depth=128

  8. Analyze FFT performance and resource utilization

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    Performance can be evaluated through two primary metrics: Throughput and Resource Utilization.

    Throughput Analysis

    • GUI: Open the co-simulation report in the Vitis GUI and verify the Initiation Interval (II) numbers for the fft_top function.
    • Waveform: Use the timeline trace viewer in Vitis or launch the Vivado waveform viewer (if the dump trace option is enabled).

    Resource Utilization and Timing

    All designs are targeted for a 2ns clock constraint (500 MHz) on a Versal device (xcvc1902-vsva2197-2MP-e-S).

    Observations:

    • Data Type Impact: Floating-point and SSR2 designs require significantly more resources (e.g., ~7x more DSPs compared to 16-bit integer designs).
    • Interface Impact: There are minimal resource differences between array and stream interfaces within the same data type category.
    • SSR Impact: SSR2 implementations achieve roughly 2x throughput improvement at the cost of increased area.

  10. Run the FFT design examples

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    To run the FFT design examples, first set up your Vitis tools in the terminal. Navigate to the example directory and use one of the following methods:

    Method 1: Using the Python script (Recommended)

    Run the run.py script to execute the full flow (csimulation, csynthesis, cosimulation, and implementation):

    $ vitis --source run.py

    After the script completes, you can open the component in the Vitis Unified IDE by running:

    $ vitis -w work_<testcase>

    (Note: Replace <testcase> with the specific design name, e.g., work_interface_array).

    Method 2: Using the Tcl script

    Alternatively, use the provided Tcl script to run the flow and create a component for the Vitis IDE:

    $ vitis-run --mode hls --tcl run_hls.tcl
    $ vitis --source run.py