Overview of Model Runner V2 (MRV2) design
mainModel Runner V2 (MRV2) is a redesigned execution core for vLLM, built from first principles to improve efficiency, modularity, and asynchronous performance. It replaces the V1 architecture by introducing several key improvements:
- Persistent Batching: Decouples persistent state from per-step inputs to simplify bookkeeping and reduce CPU overhead.
- Async-First Architecture: Designed to overlap CPU preparation and GPU execution without blocking or explicit synchronization barriers.
- GPU-Native Operations: Uses Triton kernels for input metadata preparation (e.g.,
input_ids,positions) and sampling, reducing Python bottlenecks. - Staged Writes: Uses
StagedWriteTensorfor efficient, non-blocking updates of large tensors like block tables. - Explicit CUDA Graph Management: Uses a dedicated
CUDAGraphManagerfor more predictable lifecycle and execution control. - Improved Speculative Decoding: Supports fused multi-step draft decoding and more efficient sampling via Triton kernels.