repository·master·Indexed 19 days ago
https://github.com/umd-memsys/dramsim3A cycle-accurate, thermal-capable DRAM simulator that models timing parameters and memory controller behavior for various DRAM protocols. It supports integration with CPU simulators like gem5 and ZSim, trace-based workloads, and provides tools for visualizing statistics and validating against Verilog models.
To use DRAMsim3 within the gem5 simulator, use the following command-line arguments in your gem5 execution:
--mem-type=dramsim3 --dramsim3-ini=<path_to_config_ini>
Note: This integration works with a specific fork of gem5. For reference, see the dramsim3 branch at https://github.com/umd-memsys/gem5.
--mem-type=dramsim3 --dramsim3-ini=configs/DDR4_4Gb_x4_2133.iniDRAMsim3 uses a CMake-based build system (requires CMake 3.0+). It is recommended to perform an out-of-source build to keep the source directory clean.
To build the standard library and executables:
build directory.cmake ...make -j4.By default, this creates the dramsim3main executable in the build directory and libdramsim3.so in the project root.
To build with the thermal module enabled, use the -DTHERMAL=1 flag during the CMake configuration step.
# cmake out of source build
mkdir build
cd build
cmake ..
# Build dramsim3 library and executables
make -j4
# Alternatively, build with thermal module enabled
cmake .. -DTHERMAL=1The dramsim3main executable is used to run simulations. You can run different types of workloads using configuration files (.ini) and specific flags.
-c <count>: Number of cycles/requests.-t <file>: Path to a trace file.-o <dir>: Direct output to a specific directory.--stream <type>: Specify the stream type (e.g., random).# help
./build/dramsim3main -h
# Running random stream with a config file
./build/dramsim3main configs/DDR4_8Gb_x8_3200.ini --stream random -c 100000
# Running a trace file
./build/dramsim3main configs/DDR4_8Gb_x8_3200.ini -c 100000 -t sample_trace.txtTo validate DRAMsim3 against a Verilog model (like Micron's), you must first generate a DRAM command trace.
CMD_TRACE flag enabled:
cmake .. -DCMD_TRACE=1cmd.trace file.scripts/validation.py to create a ModelSim-compatible Verilog workbench. Supported configs include DDR3, DDR4, and LPDDR.Example command:
./script/validataion.py <config_file> <trace_file>
./script/validataion.py DDR4.ini cmd.traceThe Controller uses the RowBufPolicy enum to determine how rows are managed in the DRAM banks. This affects performance based on access patterns.
Available policies:
OPEN_PAGE: Keeps the row open after an access to improve latency for subsequent accesses to the same row.CLOSE_PAGE: Closes the row immediately after an access.SIZE: (Internal/Context dependent) typically used to determine the policy based on configuration parameters.The Config class contains numerous parameters used to define the hardware model. Key categories include:
protocol, channels, ranks, banks, bankgroups, rows, columns, device_width, bus_width, and BL (Burst Length).tCK), CAS latency (CL), CAS write latency (CWL), row precharge (tRP), row activation (tRCD), and refresh timing (tRFC, tREFI).shift_bits, ch_pos, ra_pos, bg_pos, ba_pos, ro_pos, and co_pos define how physical addresses are mapped to memory components.act_energy_inc (activation), read_energy_inc, write_energy_inc, and ref_energy_inc (refresh).You can visualize simulation results using the scripts/plot_stats.py utility. This requires matplotlib to be installed in your Python environment.
dramsim3.json to generate histograms.dramsim3epoch.json to generate time series for various statistics.Note: Statistics from all channels are aggregated (squashed) for cleaner plotting.
# generate histograms from overall output
python3 scripts/plot_stats dramsim3.json
# or
# generate time series for a variety stats from epoch outputs
python3 scripts/plot_stats dramsim3epoch.jsonThe Config class allows tuning of the simulator's internal logic and system-level behavior through the following keys:
address_mapping, queue_structure, row_buf_policy, and refresh_policy.cmd_queue_size, unified_queue (bool), trans_queue_size, and write_buf_size.enable_self_refresh (bool) and sref_threshold.aggressive_precharging_enabled (bool) and enable_hbm_dual_cmd (bool).Control how the simulator writes its results using these configuration parameters:
output_dir: Directory where output files are stored.output_prefix: Prefix for output filenames.output_level: Verbosity/level of output.json_stats_name: Filename for JSON statistics.json_epoch_name: Filename for JSON epoch-based statistics.txt_stats_name: Filename for text-based statistics.If the simulator is built with the THERMAL flag enabled, the Config class includes additional parameters for thermal modeling:
chip_dim_x, chip_dim_y, mat_dim_x, mat_dim_y.num_x_grids, num_y_grids, row_tile, tile_row_num.amb_temp (ambient temperature in Celsius), const_logic_power, bank_asr (aspect ratio).bank_order (0 for x-direction priority, 1 for y-direction) and bank_layer_order (0 for low-layer priority, 1 for high-layer).When interacting with the HMCMemorySystem at a low level, use these structures to define and track HMC transactions.
HMCRequest contains:
type: The HMCReqType.mem_operand: The data/immediate value.hex_addr: The memory address.vault: The target vault.is_write: Boolean indicating if the request is a write.exit_time: The timestamp when the request exits the crossbar to the vaults.HMCResponse contains:
resp_id: Unique identifier for the response.type: The HMCRespType.link/quad: Routing information.exit_time: The timestamp when the response exits the crossbar to the CPU.The SimpleStats class in the dramsim3 namespace is used to collect, track, and report simulation statistics such as counters, vectored counters, and histograms. It supports both epoch-based (periodic) reporting and final summary reporting.
Key capabilities include:
Increment(name).IncrementVec(name, pos) or IncrementVecBy(name, pos, num).AddValue(name, value).PrintEpochStats() or the entire simulation via PrintFinalStats().Reset() to clear epoch-specific counters, typically when transitioning between simulation phases.// Example usage of SimpleStats
dramsim3::SimpleStats stats(config, channel_id);
// Increment a standard counter
stats.Increment("total_requests");
// Increment a vectored counter (e.g., per-bank index)
stats.IncrementVec("bank_accesses", bank_index);
// Increment a vectored counter by a specific amount
stats.IncrementVecBy("bank_accesses", bank_index, 5);
// Add a value to a histogram
stats.AddValue("latency_histogram", latency_value);
// Report statistics
stats.PrintEpochStats();
stats.PrintFinalStats();
// Reset epoch-specific data
stats.Reset();