Understand the edge264 architecture and programming techniques
masteredge264 uses several specialized programming techniques to optimize for performance and code size, aiming to fit within L1 cache and reduce branch predictor pressure. Key architectural patterns include:
- Single Header Definition: The file
src/edge264_internal.his the central source of truth. It contains all struct definitions, constants, enums, SIMD aliases, inline functions, macros, and exported functions. Developers should consult this file first to understand the codebase. - Code Blocks as a Pipeline: Instead of traditional deep function hierarchies, the main decoding loop is a forward pipeline designed as a Directed Acyclic Graph (DAG). Nodes are non-inlined functions and edges are tail calls, which helps mutualize code branches and reduce code size.
- Structure of Arrays (SoA): The frame buffer uses the Structure of Arrays pattern (storing arrays for each distinct field rather than an array of structures). This allows operations on frames to be expressed efficiently using bitwise and vector operators.
- SIMD Strategy: The project uses a multiarch approach combining GCC vector extensions with aliased Intel intrinsics. This allows supporting both Intel SSE and ARM NEON with ~80% common code. Some critical algorithms use 'Register-saturating SIMD', intentionally saturating the register bank to improve scaling on later CPUs.
- Bitstream Handling: Uses a 'Piston cached bitstream reader' (
src/edge264_bitstream.c) which reads bits into asize_t[2]intermediate cache, allowing 32/64 bit access per read and wide memory refills. It also performs 'On-the-fly SIMD unescaping' to avoid a separate preprocessing pass. - Error Handling: Employs 'Deferred error checking' (
src/edge264_headers.c). Rather than checking every value, it clamps inputs to expected ranges and verifies the presence ofrbsp_trailing_bitto catch corruption with high probability.