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OpenROAD Flow Scripts (ORFS)

repository·master·Indexed 20 days ago

https://github.com/the-openroad-project/openroad-flow-scripts

An autonomous RTL-to-GDSII digital implementation flow providing a complete path from hardware description language to physical layout. It supports automated exploration and manual fine-tuning via Tcl and Python, featuring integration with Bazel for building designs and a GUI for visualizing stages such as synthesis, floorplanning, placement, and global routing.

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What's inside openroad-flow-scripts

  5. Overview of the black_parrot_2019_03_28 design

    master

    The black_parrot_2019_03_28 design is a full 64-bit RISC-V core that includes a Cache Coherence Directory. This specific implementation in the OpenROAD Flow Scripts repository includes several modifications to the original source to make it suitable for the flow:

    • Memory Generation: Uses bsg_fakeram for nangate45 technology.
    • Memory Hardening: Memory blocks have been hardened.
    • Timing: Timing constraints have been added to the design.

  7. Overview of the black_parrot_2019_03_11 design

    master

    The black_parrot_2019_03_11 design is a full 64-bit RISC-V core that includes a Cache Coherence Directory. This specific implementation in the OpenROAD Flow Scripts repository has been modified from its original source to include:

    • Memory generation using bsg_fakeram for the nangate45 process.
    • Hardened memory blocks.
    • Added timing constraints.

  8. Overview of IHP SG13G2 Platform

    master

    The IHP SG13G2 is a 130 nm BiCMOS open PDK. It includes standard CMOS logic cells, heterojunction bipolar transistors (HBTs), RF MOS devices, MIM capacitors, spiral inductors, and ESD protection structures.

    Electrical Specifications:

    • Core Supply Voltage: 1.2 V
    • I/O Ring Voltage: 3.3 V

    Metal Stack Details:

    • Routing Layers: 7 layers total.
    • Default Digital Routing: Metal2 through Metal5.
    • Manufacturing Grid: 0.005 µm.
    • Padframe Routing: Designs using a padframe typically extend routing up to TopMetal2 to connect the PDN ring to IO power pads.

  11. Overview of the SweRV RISC-V Core design

    master

    The swerv design in OpenROAD Flow Scripts provides a implementation of the SweRV RISC-V Core 1.1 from Western Digital. This design is used as a reference or target for running the OpenROAD Flow.

    Note that this specific implementation includes modifications to the original source, such as default configurations from the repository, added timing constraints, and an included LICENSE file.

  12. Overview of the Ethernet MAC (ethmac) core

    master

    The ethmac core is an Ethernet Media Access Control (MAC) implementation designed for CSMA/CD LAN in accordance with IEEE 802.3 standards. It operates at the Data Link Layer of the OSI model and is responsible for:

    • Frame Data Encapsulation and Decapsulation
    • Frame Transmission
    • Frame Reception

    Technical Specifications:

    • Estimated Size: ~28k gates (approximately 2400 flip-flops).
    • Origin: Based on the OpenCores project (https://opencores.org/projects/ethmac).
    • Modifications in this repository: Includes added SDC (Synopsys Design Constraints) timing constraints and a LICENSE file.