OpenROAD Documentation

The gpl module in OpenROAD provides global placement capabilities based on the open-source RePlAce tool. It uses an analytic and nonlinear placement algorithm that solves electrostatic force equations via Nesterov's method.

Key features include:

• Mixed-size placement mode: Supports placement of cells with varying sizes.
• Technology Verification: Verified across multiple process nodes (7/14/16/28/45/55/65nm) using OpenDB.
• Determinism: Guaranteed deterministic solution generation across different compilers and operating systems.

FastRoute is a global routing tool designed for VLSI back-end design. It utilizes a sequential rip-up and re-route (RRR) methodology combined with several advanced techniques to manage congestion and via counts.

Key evolutionary features include:

• Steiner Tree Construction: Uses FLUTE to construct congestion-driven Steiner trees, followed by edge shifting to optimize tree structure.
• Congestion Management: Employs pattern routing, maze routing with logistic function-based cost functions, and monotonic routing.
• Virtual Capacity: Uses a virtual capacity technique to adaptively adjust edge capacities, diverting wire usage from congested to less congested regions.
• Via Minimization: Features via-aware Steiner trees, 3-bend routing, and layer assignment algorithms to reduce via counts.

OpenROAD provides an autonomous, No-Human-In-Loop (NHIL) flow that converts Verilog RTL, libraries, and constraints into a final GDSII layout. The flow consists of the following stages:

1. Synthesis: Converts Verilog to a netlist.
2. Floorplan: Initializes chip area, performs IO placement, tapcell/welltie insertion, and PDN generation.
3. Placement: Includes global placement (macro and standard cell) and detailed placement (legalization and timing analysis).
4. Clock Tree Synthesis (CTS): Inserts buffers and resizes nets for timing optimization.
5. Routing: Performs global and detailed routing (DRC-correct).
6. Finishing: Includes parasitic extraction (OpenRCX), final timing/physical verification, and dummy metal fill.

The Pin Placer is a tool used to place pins on the die boundary along the track grid. Its primary goals are to minimize net wirelengths and create metal shapes for each pin based on min-area rules.

For designs containing unplaced cells, the tool calculates net wirelength by assuming the unplaced cells are positioned at the center of the die area.

The rcx module in OpenROAD is based on OpenRCX, an open-source Parasitic Extraction (PEX) tool that utilizes OpenDB design APIs. It extracts both Resistance and Capacitance for routed designs based on the LEF/DEF layout model.

Key features include:

• Extraction Scope: Extracts resistance and capacitance for wires based on coupling distance, track density context, and cell abstracts.
• Accuracy: Uses an Extraction Rules file (RC technology file) containing equations and calibration measurements for a specific process node and corner.
• Data Storage: Stores resistance, coupling capacitance, and ground capacitance directly on OpenDB objects with pointers to the associated wire and via db objects.
• Output: Supports generating .spef files.

The gen.py script orchestrates the code generation process through four distinct stages:

1. load_schema(): Reads the top-level schema.json and all individual class files located in schema/**/*.json.
2. process_schema(): Performs derivation logic, including expanding relations, classifying field types, resolving accessor names/includes, packing bitfields, and computing comparison operators.
3. generate(): Renders the derived data into C++ and CMake files using Jinja2 templates located in the templates/ directory.
4. _merge_files(): Splicing stage. It inserts the generated code into the actual source files while preserving hand-written User Code blocks, followed by a clang-format pass.