stm32l4xx-hal

The Pins<USART> trait is used by the HAL to detect the capabilities of your pin configuration, such as whether hardware flow control, RS485 (DEM) mode, or half-duplex mode is enabled. You can provide different tuples of pins to satisfy different hardware requirements:

• Standard Rx+Tx: Use a tuple (Tx, Rx). Sets FLOWCTL, DEM, and HALF_DUPLEX to false.
• Half-Duplex (Tx only): Use a tuple (Tx,) where Tx implements TxHalfDuplexPin. Sets HALF_DUPLEX to true.
• Hardware Flow Control: Use a tuple (Tx, Rx, Rts, Cts) where pins implement TxPin, RxPin, RtsDePin, and CtsPin. Sets FLOWCTL to true.
• RS485 Mode (DEM): Use a tuple (Tx, Rx, De) where De implements RtsDePin. Sets DEM to true.

// Example conceptual usage of pin tuples for different modes
// Note: Actual instantiation depends on specific peripheral and pin types

// Standard mode
let pins = (tx_pin, rx_pin);

// Half-duplex mode
let pins = (tx_pin,);

// Hardware flow control mode
let pins = (tx_pin, rx_pin, rts_pin, cts_pin);

// RS485 mode
let pins = (tx_pin, rx_pin, de_pin);

To program the flash memory, you must first unlock the flash registers using the KEYR register. This returns a FlashProgramming object which provides an interface for erasing and writing data. The FlashProgramming object automatically locks the flash controller when it is dropped.

Workflow

1. Constrain the FLASH peripheral: Use FlashExt::constrain() on the raw FLASH peripheral to get a Parts struct containing the necessary registers.
2. Unlock: Call keyr.unlock_flash(&mut sr, &mut cr) to obtain a FlashProgramming instance.
3. Erase: Use erase_page(page) to clear a specific page.
4. Write: Use write(address, data) for byte-oriented writes or write_native(address, data) for high-performance u64 writes.

Warning: erase_all_pages() will erase the entire flash, including the currently running program. This should only be called if the program is running from RAM.

fn program_region(mut flash: flash::Parts) -> Result<(), flash::Error> {
    // Unlock the flashing module
    let mut prog = flash.keyr.unlock_flash(&mut flash.sr, &mut flash.cr)?;

    let page = flash::FlashPage(5);

    // Perform the erase and programming operation
    prog.erase_page(page)?;
    let data = [
        0x1111_1112_1113_1114,
        0x2221_2222_2223_2224,
        0x3331_3332_3333_3334,
    ];
    prog.write_native(page.to_address(), &data)?;

    // Check result
    let addr = page.to_address() as *const u64;
    assert!(unsafe { core::ptr::read(addr) } == data[0]);
    assert!(unsafe { core::ptr::read(addr.offset(1)) } == data[1]);
    assert!(unsafe { core::ptr::read(addr.offset(2)) } == data[2]);

    Ok(())
}

The CFGR (Clock Configuration Register) builder allows you to define the desired clock tree for your STM32L4 device. Once configured, you must call .freeze() to apply the settings.

Note: .freeze() requires mutable references to the ACR (Flash Access Control Register) and Pwr (Power Control) peripherals to adjust flash latency and unlock the backup domain if necessary.

Common configuration methods include:

• .sysclk(freq): Sets the system (core) frequency.
• .hclk(freq): Sets the AHB bus frequency.
• .pclk1(freq) / .pclk2(freq): Sets APB bus frequencies.
• .msi(range): Sets the Multi-Speed Internal clock frequency using MsiFreq.
• .hse(freq, bypass, css): Configures the High-Speed External clock.
• .lse(bypass, css): Configures the Low-Speed External clock.
• .hsi48(bool): Enables the 48 MHz HSI clock for USB/RNG/SDMMC.
• .sysclk_with_pll(freq, pll_config): Sets the system frequency using a specific PLL configuration.

let clocks = rcc.cfgr
    .sysclk(80.MHz()
    .hclk(80.MHz())
    .pclk1(40.MHz())
    .pclk2(80.MHz())
    .freeze(&mut flash.acr, &mut pwr);

When using DMA for serial communication, you can use FrameReader and FrameSender to manage the lifecycle of data frames.

FrameSender (Transmitting)

• send(frame): Starts a new DMA transfer with the provided buffer. Returns Err(frame) if a transfer is already in progress.
• transfer_complete_interrupt(): Should be called inside the DMA Transfer Complete interrupt. It clears the interrupt and returns the Option<BUFFER> (the frame used for the transfer) so you can reuse or free it.
• ongoing_transfer(): Returns true if a transmission is currently active.

FrameReader (Receiving)

FrameReader handles incoming data and can be triggered by different interrupt types:

• transfer_complete_interrupt(next_frame): Called when the DMA transfer finishes.
• character_match_interrupt(next_frame): Called when a specific character is matched (e.g., in USART).
• receiver_timeout_interrupt(next_frame): Called when a receiver timeout occurs.

All these methods return the BUFFER that was being used for the previous transfer, allowing for continuous frame rotation.

// Example conceptual flow for a Sender
if let Err(old_frame) = sender.send(new_frame) { 
    // Handle busy state
}

// Inside DMA Interrupt
if let Some(completed_frame) = sender.transfer_complete_interrupt() {
    // Process completed_frame
}

The LowPowerTimer supports two interrupt events:

1. Event::CompareMatch: Occurs when the counter matches the compare value.
2. Event::AutoReloadMatch: Occurs when the counter reaches the auto-reload value (the counter is then reset to 0).

Workflow for handling interrupts:

1. Enable listening: Call .listen(event) to enable interrupts for a specific event.
2. Check trigger status: In your interrupt handler or main loop, call .is_event_triggered(event) to check if the event occurred.
3. Clear flag: If is_event_triggered returns true, you must call .clear_event_flag(event) to prevent the interrupt from firing continuously.
4. Disable listening: Call .unlisten(event) to stop receiving interrupts for that event.

// Enable compare match interrupt
lptim1.listen(Event::CompareMatch);

// In an interrupt handler or polling loop:
if lptim1.is_event_triggered(Event::CompareMatch) {
    lptim1.clear_event_flag(Event::CompareMatch);
    // Handle the event...
}