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CrossSim Accuracy Simulator

repository·main·Indexed 42 days ago

https://github.com/sandialabs/cross-sim

A GPU-accelerated, Python-based crossbar simulator for modeling analog in-memory computing. Version 3.2.1 serves as an accuracy simulator and co-design tool to evaluate the impact of analog hardware non-idealities, such as conductance drift and ADC precision loss, on neural networks and signal processing algorithms. It includes interfaces for Keras and PyTorch, and provides native support for use within Matlab.

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What's inside CrossSim

  1. Overview of the simulator.parameters package

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    The simulator.parameters package is the central location for managing configuration and parameterization within CrossSim. It is organized into several submodules that categorize parameters based on their function in the simulation pipeline:

    • base_parameters: Fundamental parameter types used across the simulator.
    • core_parameters: Core simulation settings and engine configurations.
    • crosssim_parameters: Parameters specific to the CrossSim implementation logic.
    • simulation_parameters: High-level parameters governing the execution of a simulation run.
    • xbar_parameters: Parameters defining crossbar (xbar) hardware characteristics and behavior.

  2. Explore CrossSim circuit models

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    The circuits directory contains models representing the behavior of MVM/VMM (Matrix-Vector Multiplication/Vector-Matrix Multiplication) crossbar arrays and their associated peripheral circuitry.

    To model specific components, navigate to the following subdirectories:

    • ADCs/DACs: For models of Analog-to-Digital Converters and Digital-to-Analog Converters, refer to the documentation in the adc and dac directories.
    • Array Circuit Simulator: For the core array circuit simulation logic, refer to the documentation in the array directory.

  3. Explore the simulator.circuits package structure

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    The simulator.circuits package provides tools for simulating circuit-level components in neural network inference. It is organized into subpackages for specific component types and a main module for array-level simulation.

    Core Subpackages:

    • simulator.circuits.adc: Contains Analog-to-Digital Converter (ADC) models.
    • simulator.circuits.dac: Contains Digital-to-Analog Converter (DAC) models.

    Core Modules:

    • simulator.circuits.array_simulator: The primary module for simulating crossbar arrays or similar circuit structures.

  4. Explore the CrossSim simulator package structure

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    The simulator package is the core entry point for CrossSim. It is organized into several specialized subpackages that handle different aspects of the simulation lifecycle:

    • simulator.algorithms: Contains simulation algorithms.
    • simulator.backend: Manages the computational backend.
    • simulator.circuits: Handles circuit-level simulations.
    • simulator.configs: Manages configuration objects and settings.
    • simulator.cores: Defines core simulation logic.
    • simulator.devices: Contains device models and hardware abstractions.
    • simulator.parameters: Manages simulation parameters.

  5. Overview of the simulator.cores package

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    The simulator.cores package provides various core simulation modules for CrossSim. These modules implement different simulation strategies for neural network inference, ranging from high-precision numeric simulations to hardware-aware analog and bitsliced models. Users select a core based on the level of hardware non-ideality and computational complexity they wish to simulate.

  6. Understand the CrossSim Core hierarchy

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    CrossSim uses a three-level hierarchy of cores to represent analog in-memory computing arrays. The hierarchy moves from high-level software-friendly abstractions to low-level physical hardware models:

    1. AnalogCore (Highest Level): Designed to behave like a Numpy array. It handles arbitrary matrix sizes, complex-valued operands, and automatically partitions large matrices into smaller constituent cores.
    2. Intermediate Cores (BalancedCore, OffsetCore, BitSlicedCore): These manage how numerical values (including negative numbers and high precision) are mapped to physical conductance. They handle the logic of bit-slicing and sign representation.
    3. NumericCore (Lowest Level): Represents a single physical resistive crossbar. It interfaces directly with device models (for noise, drift, and programming errors) and circuit solvers (for parasitic resistance effects).

  7. Choose between Generic and Circuit-based ADC models

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    CrossSim provides two categories of ADC models depending on whether you need ideal quantization or physical non-ideality modeling:

    Generic ADC Models (Ideal)

    These implement standard quantization behavior without component errors:

    • QuantizerADC: Rounds input to $2^N$ levels between min and max (where $N$ is bit resolution). Min/max do not need to be symmetric.
    • SignMagnitudeADC: Assumes sign-magnitude representation. Min/max must be symmetric about zero, and there are $2^{(N-1)}$ levels due to redundant zero representations.

    Circuit-based ADC Models (Non-ideal)

    These use analytical equations to model physical circuits (switched capacitors, op-amps, comparators) and include non-idealities like capacitor mismatch, comparator offset, and finite amplifier gain. Available models:

    • RampADC (Ramp ADC)
    • SarADC (Successive Approximation Register ADC)
    • PipelineADC (Pipeline ADC)
    • CyclicADC (Cyclic ADC)

  8. How CrossSim neural network integrations work

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    CrossSim provides neural network layer implementations that wrap the AnalogCore simulator interface. These layers are designed to be instantiated by high-level frameworks like PyTorch or Keras rather than being used directly.

    Key architectural details:

    • AnalogCore Mapping: Each layer implementation typically assumes a single AnalogCore, though layers can be partitioned across multiple arrays within a single core.
    • Complex Operations: Certain operations, such as convolutions, are implemented using multiple Matrix-Vector Multiplication (MVM) operations combined with internal buffering and indexing.
    • Convention: Layer implementations follow PyTorch conventions for parameter naming and dimension ordering.

  9. Use the UncoupledNonlinearArray model

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    The UncoupledNonlinearArray model is a specialized, high-performance model used only when specific conditions are met:

    1. Device I-V nonlinearity is enabled.
    2. Parasitic resistance is disabled.
    3. Each summation line is held at a virtual ground.

    Under these conditions, device currents are uncoupled, meaning an iterative solver is not required. The model directly calls the device I-V nonlinearity model to compute cell currents or summed currents for the applied voltages.

  10. Implement custom ADC models using ADCParameters

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    When creating custom Analog-to-Digital Converter (ADC) models, your parameter class should inherit from the ADCParameters class. This ensures that common parameters, such as the number of bits of resolution, are consistently implemented across different ADC types.

    Example inheritance pattern:

    • RampADCParameters inherits from ADCParameters
    • SarADCParameters inherits from ADCParameters

  11. How DAC models work and their available functions

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    DAC models are controlled via the DACParameters class (using params.xbar.dac.mvm or params.xbar.dac.vmm). All DAC models inherit from the IDAC base class and implement the following three functions:

    1. set_limits: Sets the minimum and maximum output values. These should correspond to the ranges defined in params.core.mapping.inputs.mvm.min.
    2. convert: Quantizes input vector values to equally spaced levels within the set range. The number of levels is determined by the bit resolution specified in dac_params.bits.
    3. convert_sliced: Implements input bit slicing. This quantizes the input vector and returns a list of vectors representing the input bit slices.
      • The bit width of a slice is controlled by dac_params.slice_size.
      • Values in a slice are one of $2^B$ discrete values between 0 and 1, where $B$ is the slice size.
      • Physically, this represents time-multiplexing different bit slices of digital input into the DAC to compute analog MVMs one slice at a time.

  12. How CrossSim parameters are structured

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    CrossSim uses a hierarchical parameter infrastructure consolidated into a single CrossSimParameters object. This object categorizes settings into three main branches, which can further be subdivided into nested groups:

    1. Core parameters (CoreParameters): Configure how data (matrix weights, vector inputs) maps to hardware and the numerical range of representable values.
    2. Crossbar parameters (XbarParameters): Configure resistive device models, memory array electrical topology, parasitics, and peripheral circuits (e.g., ADCs and DACs).
    3. Simulation parameters (SimulationParameters): Configure numerical simulation settings such as GPU usage, circuit solver convergence, data profiling, and performance.

    All parameter objects inherit from BaseParameters, which provides the interface for importing from or exporting to JSON files.

    params = CrossSimParameters()
# Accessing a nested parameter via hierarchy
params.xbar.array.parasitics.Rp_col = 1