Overview of RTLLM × ShinkaEvolve PPA Optimization
mainThis project uses ShinkaEvolve to optimize Verilog designs for PPA (Power, Performance, and Area) while keeping the functional specification fixed.
Instead of a binary pass/fail correctness score, the fitness function is a continuous score based on the geometric mean of speedups over a human-designed reference:
score = 100 · geomean( area_ref/area_cand , depth_ref/depth_cand , power_ref/power_cand )
A reference design scores 100. A correct implementation that is smaller, faster, or lower-power will score > 100.
Metrics measured:
- Area (µm²): Measured via Yosys using Nangate45 standard cells (
stat -liberty). - Performance (logic depth): Measured via Yosys longest topological path (
ltp). - Power (µW): Measured via OpenSTA on the gate-level netlist (
report_power). - Correctness: Verified via Icarus Verilog (testbench) and Yosys formal equivalence (
equiv/sat) to ensure the candidate matches the reference function.