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RISC-V Instruction Set Manual

repository·main·Indexed 26 days ago

https://github.com/riscv/riscv-isa-manual

Official source files and specifications for the RISC-V Instruction Set Manual, comprising Volume I: Unprivileged Architecture, Volume II: Privileged Architecture, and Volume III: Profiles. The repository includes normative rule definitions, marchid CSR values, and detailed specifications for base integer instruction sets (RV32I, RV64I), standard extensions (M, A, C, V, B), floating-point extensions (F, D, Q), and privileged machine modes.

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What's inside riscv-isa-manual

  1. Overview of Hypervisor Extensions (ext:sh[])

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    The ext:sh[] Hypervisor Extensions define the architectural requirements for hypervisor support in RISC-V. This extension includes several sub-components that manage trap/exception handling, virtual memory, and address translation for virtualized environments.

    Note: This section is currently undergoing restructuring; while the contents are normative, the documentation presentation may appear disjointed.

  2. Overview of Scalar Cryptography Extensions

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    The Scalar Cryptography Extension provides lightweight instructions for 32-bit and 64-bit base architectures, ranging from embedded IoT cores to application-class cores without vector units. All instructions use general-purpose x registers and follow the 2-read-1-write register access constraint. The extension also includes an architectural interface to an Entropy Source for generating cryptographic secrets.

  3. Overview of the Zcb Extension

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    The ext:zcb extension provides additional compressed instructions that expand into single 32-bit instructions. It depends on the ext:zca extension. Many instructions within ext:zcb have additional prerequisites, such as requiring the ext:m, ext:zmmul, or ext:zbb extensions to be implemented.

  4. Overview of Control Transfer Records (CTR) Extension

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    The Control Transfer Records (CTR) extension (Smctr/Ssctr) provides a method for recording a limited history of control flow transfers (jumps, calls, returns, branches, and traps) in register-accessible internal chip storage. This is designed to reduce the performance overhead and complexity of collecting transfer history compared to full trace capabilities.

    Key features include:

    • A circular (FIFO) buffer of records.
    • Support for RAS (Return Address Stack) emulation mode.
    • Indirect CSR interface for accessing logical buffer entries.
    • Filtering of transfers based on privilege mode and transfer type.

  6. Overview of the Zcmp extension

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    The ext:zcmp[] extension provides instructions designed to reduce the static code size of procedure prologues and epilogues. It introduces a set of instructions collectively referred to as insn:push[]/insn:pop[]:

    • insn:cm.push[] (referred to as insn:push[])
    • insn:cm.pop[] (referred to as insn:pop[])
    • insn:cm.popret[] and insn:cm.popretz[] (referred to as insn:popret[])

    These instructions automate stack pointer (sp) adjustment and register saving/restoring, which can significantly reduce code size compared to standard instruction sequences or millicode calls.

  7. Overview of the ext:zcmt[] Extension

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    The ext:zcmt[] (Compressed Table Jumps) extension improves code density by providing table-jump instructions that replace common instruction sequences (like jal, auipc+jr, etc.) with a single instruction and a table entry.

    Key Characteristics:

    • Target: Primarily embedded class CPUs; not compatible with RVA profiles.
    • Conflicts: Conflicts with the ext:zcd[] extension.
    • Dependencies: Depends on extlink:zca[] and extlink:zicsr[].
    • Mechanism: Uses a 256-entry XLEN-wide table in instruction memory. The table must be at least 64-byte aligned.
    • Endianness: Table entries follow the current data endianness (unlike standard instruction fetches which are always little-endian).

  8. Understand the ext:ziccid[] Extension for Instruction/Data Coherence and Consistency

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    The ext:ziccid[] extension provides stricter requirements for consistency between instruction fetches and memory accesses compared to the base ISA. Its primary purpose is to accelerate JIT (Just-In-Time) compilation in multiprocessor systems by codifying instruction-cache coherence.

    Key Guarantees:

    • In-order Fetch: A hart's instruction fetches appear to occur in program order relative to each other.
    • Eventual Visibility: Stores eventually become visible to all harts' instruction fetches, even without executing a FENCE.I instruction.
    • Dependency: This extension depends on the ext:ziccif[] extension.

    Note: This operational model applies only to instruction fetches to memory regions with cacheability and coherence PMAs. Fetches to other regions behave as if the extension is not implemented.

  9. Understand the RV32I Base Integer Instruction Set

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    RV32I is the base integer instruction set for 32-bit RISC-V. It is designed to be a sufficient compiler target and support modern operating systems while minimizing hardware requirements. It contains 40 unique instructions (effectively 38 if ecall/ebreak are handled by a single trap and fence is treated as a nop). RV32I can emulate most other unprivileged ISA extensions, except those requiring additional hardware for atomicity (like ext:a or ext:za*).

  10. Use the Zicond extension for branchless conditional operations

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    The Zicond extension provides two R-type instructions designed for branchless conditional operations. These instructions allow for conditional moves of zero or a register value based on whether a condition register is zero or non-zero, which is useful for implementing conditional arithmetic, bitwise logic, and selection without branches.

  11. Use the zicntr extension for base counters and timers

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    The zicntr extension provides three 64-bit read-only performance counters accessible via unprivileged CSR registers. These counters are essential for performance analysis, dynamic optimization, and real-time stream processing.

    Available Counters:

    • cycle: Counts clock cycles executed by the processor core.
    • time: Counts wall-clock real time (ticks).
    • instret: Counts instructions retired by the hart.

    Note on Access:

    • For XLEN $\ge$ 64, the full 64-bit values are accessed directly using rdcycle, rdtime, and rdinstret.
    • For XLEN = 32, the counters are accessed in two 32-bit pieces using high/low pseudoinstructions (e.g., rdcycle for bits 31-0 and rdcycleh for bits 63-32).

  12. Understand Trap Types: Vertical and Horizontal

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    Traps are used to switch execution between privilege levels:

    • Vertical Traps: Traps that increase the privilege level (e.g., a supervisor call or timer interrupt forcing a switch from U-mode to a higher mode).
    • Horizontal Traps: Traps that remain at the same privilege level.

    RISC-V provides flexible routing for these traps, and horizontal traps can be implemented as vertical traps that return control to a handler in a less-privileged mode.