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The UVM Primer Code Examples

repository·master·Indexed 20 days ago

https://github.com/raysalemi/uvmprimer

A collection of verified and simulated code examples accompanying the book 'The UVM Primer'. The repository provides practical implementations of UVM concepts, including a TinyALU SystemVerilog implementation, with simulation scripts designed for the Questa simulator.

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What's inside uvmprimer

  1. Navigate the UVM Primer example directory structure

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    The examples are organized to correspond with the chapters and titles found in the book The UVM Primer.

    • Directories are named according to chapter numbers and titles.
    • Chapters containing multiple examples include subdirectories for each specific example.

  2. Run UVM Primer code examples with Questa simulator

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    Each example directory contains a run.do file designed to compile and execute the code using Mentor Graphics' Questa simulator.

    To run an example in command-line mode, use the following command from within the specific example directory:

    % vsim -c -do run.do

    To run the example using the Questa GUI instead of the command line, remove the -c option:

  3. Use the TinyALU SystemVerilog implementation

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    The tinyalu.sv file provides a TinyALU implementation in SystemVerilog. To use this file in the provided simulation environment, you must modify the existing run.do file. Specifically, replace the existing vcom command line with a vlog command line that compiles tinyalu.sv instead.

    # In run.do, replace the vcom line with:
vlog tinyalu.sv