PyRPL (Python RedPitaya Lockbox)

repository·main·Indexed 41 days ago

https://github.com/pyrpl-fpga/pyrpl

A software package that transforms RedPitaya/STEMlab hardware into a DSP device optimized for digital feedback control and measurement in quantum optics experiments. It provides tools for FPGA bitstream management, XADC input access via Linux IIO, and high-level modules for IQ filtering, network analysis, and Lockbox physical models for systems like Fabry Perot cavities.

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What's inside PyRPL

  1. Explore the pyrpl package structure

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    The pyrpl package is organized into several subpackages and modules that handle different aspects of the system, including hardware interaction, software modules, testing, and UI widgets.

    Subpackages

    • pyrpl.hardware_modules: Modules for interacting with hardware components.
    • pyrpl.software_modules: Modules for software-based logic and processing.
    • pyrpl.test: Testing utilities and suites.
    • pyrpl.widgets: UI components and widgets for interacting with PyRPL.

    Core Modules

    • pyrpl.pyrpl: The main entry point and core logic of the package.
    • pyrpl.acquisition_module: Handles data acquisition processes.
    • pyrpl.curvedb: Provides functionality for curve databases.
    • pyrpl.redpitaya: Specific support for Red Pitaya hardware.
    • pyrpl.redpitaya_client: Client-side interface for Red Pitaya communication.
    • pyrpl.memory: Memory management utilities.
    • pyrpl.errors: Custom error definitions and handling.
  2. Explore available pyrpl.hardware_modules

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    The pyrpl.hardware_modules package provides access to the various hardware-accelerated modules available on the FPGA. These modules are organized into submodules based on their functional purpose (e.g., signal processing, control, data acquisition).

    Available functional modules include:

    • ams: Analog Mixed Signal related modules.
    • asg: Arbitrary Signal Generator.
    • dsp: Digital Signal Processing modules.
    • filter: Hardware filtering modules (including the iir subpackage).
    • hk: Housekeeping modules.
    • iq: IQ (In-phase/Quadrature) processing modules.
    • pid: Proportional-Integral-Derivative control modules.
    • pwm: Pulse Width Modulation modules.
    • sampler: Sampling and data acquisition modules.
    • scope: Oscilloscope-like functionality.
    • trig: Triggering modules.
  3. Hardware Requirements: Red Pitaya

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    PyRPL currently only supports the Red Pitaya hardware platform.

    Red Pitaya Specifications:

    • Architecture: FPGA + CPU running a Linux operating system.
    • FPGA Clock Rate: 125 MSps.
    • Analog I/O: 2 analog inputs and 2 analog outputs (14 bits, 125 MSps).
    • Latency: Minimum input-output latency is approximately 200 ns.
    • Effective Resolution: 12 bits for inputs, 13 bits for outputs.
    • Additional I/O: 4 slow analog inputs/outputs and 16 digital I/O ports.
  4. Configure default values for SelectProperty

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    You can set a custom default value for a SelectProperty during module initialization using self.default.

    Default Value Resolution Logic

    The self.default getter follows a specific fallback hierarchy to ensure it always returns a valid element from the available options:

    1. Match Overwritten Default: It first attempts to locate the custom overwritten default value within the current options.
    2. First Option: If the custom default is not found in the options, it attempts to return the first available option.
    3. None: If no options are available, it returns None.
  5. Simulate asyncio compatibility for Python 2.7

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    If you need to provide an asynchronous-like interface while maintaining Python 2.7 compatibility (where async/await syntax is unavailable), you cannot use coroutines. Instead, you must use a callback-based pattern or a custom Future implementation that wraps a Qt timer or signal to simulate asynchronous completion.

    In PyRPL, the goal is to allow Python 3 users to use await even if the underlying implementation uses Python 2-compatible callback logic. This is achieved by returning objects that behave like asyncio.Future or concurrent.futures.Future.

    try:
        from asyncio import Future, ensure_future
    except ImportError:
        from concurrent.futures import Future
    
    class MyFuture(Future):
        def __init__(self):
            super(MyFuture, self).__init__()
            # Use Qt timers to simulate async completion
            self.timer = QtCore.QTimer()
            self.timer.timeout.connect(lambda : self.set_result(rand(100)))
            self.timer.setSingleShot(True)
            self.timer.setInterval(1000)
            self.timer.start()
    
        def result(self):
            # If not done, run a local event loop to wait
            if not self.done():
                self.loop = QtCore.QEventLoop()
                self.add_done_callback(lambda x: self.loop.quit())
                self.loop.exec_()
            return super(MyFuture, self).result()
  6. Use the Pyrpl class for high-level control

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    The Pyrpl class provides a high-level API designed to abstract away the detailed implementation of the RedPitaya hardware, allowing users to focus on experimental physics. It offers simplified methods for common tasks like locking cavities or interferometers.

    Example high-level operations:

    • cavity.lock(method='pdh', detuning=0.1): Performs an optimal PDH lock with a specific detuning.
    • cavity.unlock(): Releases the lock.
    • interferometer.lock(phase=45.0): Calibrates fringe height and locks at a specific local oscillator phase.
    # Example of high-level API usage
    cavity.lock(method='pdh', detuning=0.1)
    cavity.unlock()
    interferometer.lock(phase=45.0)
  7. Use PyRPL Module Widgets

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    The PyRPL GUI is composed of various module widgets that can be added via the "modules" menu. These widgets can be:

    • Closed or reopened at any time.
    • Docked or undocked from the main module window using drag-and-drop on their sidebar.
    • Persisted via the configuration file, which saves their positions for the next startup.

    Commonly used widgets include:

    • PID module: For control loops.
    • Acquisition Module Widgets: For data capture.
    • Scope Widget: For real-time waveform viewing.
    • Network Analyzer Widget: For measuring transfer functions.
    • Spectrum Analyzer Widget: For frequency domain analysis.
    • Iq Widget: For IQ signal visualization (includes a schematic view toggle).
    • Lockbox Widget: For lock-in detection tasks.
  8. Components of the pyrpl.software_modules.lockbox package

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    The lockbox software module is composed of the following functional units:

    • pyrpl.software_modules.lockbox.gainoptimizer: Module for optimizing gain settings.
    • pyrpl.software_modules.lockbox.input: Handles input data/signals for the lockbox.
    • pyrpl.software_modules.lockbox.lockbox: The core lockbox logic/module.
    • pyrpl.software_modules.lockbox.output: Handles output signals/actions for the lockbox.
    • pyrpl.software_modules.lockbox.stage: Manages the stages of the lockbox process.
    • pyrpl.software_modules.lockbox.models: A subpackage containing data models used by the lockbox modules.
  9. Available software modules in pyrpl.software_modules

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    The pyrpl.software_modules package is organized into several submodules, each providing specific capabilities:

    • curve_viewer: Tools for visualizing curves.
    • loop: Modules for implementing control loops.
    • module_managers: Management utilities for software modules.
    • network_analyzer: Tools for network analysis.
    • pyrpl_config: Utilities for handling PyRPL configurations.
    • software_pid: Software-based PID controllers.
    • spectrum_analyzer: Tools for spectrum analysis.
    • lockbox: (Subpackage) Specialized locking or synchronization functionality.
  10. How FPGA modules and signal routing work

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    PyRPL organizes FPGA functionalities into various Digital Signal Processing (DSP) modules. These modules can be connected arbitrarily to create complex experimental setups without recompiling the FPGA code.

    Available Modules

    ModuleDescription
    Scope16384 points, 2 channels oscilloscope
    ASGArbitrary signal generator (waveforms, Gaussian white noise)
    IQ modulator/demodulatorDigital demodulation/remodulation using an internal frequency reference
    PIDProportional/Integrator/Differential feedback (Differential gain currently disabled); includes a 4th order linear filter
    IIRInfinite Impulse Response filter for complex transfer functions
    TriggerDetects transitions on analog signals
    SamplerSamples external or internal signals
    PwmControls Red Pitaya pulse width modulation pins
    HkHousekeeping: monitors constants and controls LED status

    Connecting Modules

    Modules are connected via digital signal routing. Most modules (except ASG) contain a generic register input_select.

    • To connect submodule i to submodule j: Set the register input_select[j] to the index i.
    • Direct Output: Most modules (except Scope and Trigger) have an output_direct signal. This can be routed to analog output 1 and/or 2 using the output_select register.