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pyverilog

repository·develop·Indexed 21 days ago

https://github.com/pyhdi/pyverilog

A Python-based toolkit for processing Verilog HDL. It provides capabilities for parsing Verilog source code into an Abstract Syntax Tree (AST), dataflow analysis with signal assignment optimization, control-flow analysis for identifying state machine structures, and generating Verilog HDL code from AST instances.

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What's inside pyverilog

  1. What is Pyverilog?

    develop

    Pyverilog is a Python-based hardware design processing toolkit for Verilog HDL. It provides four core capabilities:

    1. Code Parser: Generates an Abstract Syntax Tree (AST) from Verilog source code.
    2. Dataflow Analyzer: Analyzes signal assignments and includes an optimizer to remove redundant expressions.
    3. Control-flow Analyzer: Identifies state machine structures and signal activation conditions.
    4. Code Generator: Generates Verilog HDL code from AST instances.

  2. Install Pyverilog and its requirements

    develop

    To use Pyverilog, you must install Python 3.7+ and Icarus Verilog 10.1+. You also need jinja2 and ply as Python dependencies.

    Core Requirements

    1. Icarus Verilog: sudo apt install iverilog
    2. Python Dependencies: pip3 install jinja2 ply

    Optional Dependencies

    • For Testing: pip3 install pytest pytest-pythonpath
    • For Visualization (Graphviz/Pygraphviz): sudo apt install graphviz and pip3 install pygraphviz

    Installation

    Once requirements are met, install the package using the setup script:

    python3 setup.py install
    sudo apt install iverilog
pip3 install jinja2 ply
python3 setup.py install

  3. Generate Verilog HDL code from AST

    develop

    To generate Verilog code, you must programmatically construct AST objects using the classes in pyverilog.vparser.ast and then pass them to the ASTCodeGenerator.

    import pyverilog.vparser.ast as vast
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator

# ... construct AST objects (ModuleDef, Portlist, etc.) ...

# Example snippet for generating code from an AST object 'ast'
codegen = ASTCodeGenerator()
rslt = codegen.visit(ast)
print(rslt)

  4. Use the Control-flow Analyzer

    develop

    The control-flow analyzer identifies Finite State Machine (FSM) structures and transition conditions.

    Command Line Usage

    python3 pyverilog/examples/example_controlflow_analyzer.py -t <top_module_name> <verilog_file>

    Note: If Graphviz is not installed, append the --nograph option to avoid errors.

    python3 pyverilog/examples/example_controlflow_analyzer.py -t top test.v

  5. Use the Dataflow Analyzer

    develop

    The dataflow analyzer identifies signal definitions and assignments. You can specify the top module using the -t flag.

    Command Line Usage

    python3 pyverilog/examples/example_dataflow_analyzer.py -t <top_module_name> <verilog_file>

    Visualizing Dataflow

    If Graphviz and Pygraphviz are installed, you can generate a PNG image of the dataflow for a specific signal using example_graphgen.py:

    python3 pyverilog/examples/example_graphgen.py -t <top_module_name> -s <top_module_name>.<signal_name> <verilog_file>
    # Analyze dataflow
python3 pyverilog/examples/example_dataflow_analyzer.py -t top test.v 

# Generate dataflow graph for signal 'top.led'
python3 pyverilog/examples/example_graphgen.py -t top -s top.led test.v

  6. Use the Code Parser (vparser) to generate an AST

    develop

    You can perform syntax analysis on a Verilog file using the example_parser.py script. This will output a hierarchical representation of the module, ports, declarations, and assignments.

    python3 pyverilog/examples/example_parser.py test.v