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CH32V307 RISC-V MCU Documentation

repository·main·Indexed 19 days ago

https://github.com/openwch/ch32v307

Resources for the CH32V307 32-bit interconnected RISC-V MCU, featuring a RISC-V4F core (max 144MHz), hardware FPU, and high-speed connectivity including USB 2.0 (480Mbps) and GbE Ethernet MAC. The repository provides access to official datasheets, reference manuals, QingKe V4 processor documentation, EVT development board schematics (R0-1v0 and R1-1v0), and software examples for FreeRTOS, IoCHub, and C11 Annex K bounds-checking functions.

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What's inside CH32V307

  1. Overview of bounds_checking_function

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    The bounds_checking_function library provides implementations of common memory and string manipulation functions that adhere to the C11 Annex K (Bounds-checking interfaces) standard. It is designed to improve memory safety by providing safer alternatives to standard C functions, such as memcpy_s and strcpy_s, which include explicit bounds checking to prevent buffer overflows.

    Key features include:

    • Implementation of common memory/string operation functions (e.g., memcpy_s, strcpy_s).
    • Compliance with C11 Annex K standards.
    • Ongoing analysis and potential implementation of additional standard functions defined in Annex K.

  2. Overview of the CH32V307V-R0-1v0 EVT development board

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    The CH32V307V-R0-1v0 is an Engineering Verification Test (EVT) development board designed for the CH32V307 series, which is a 32-bit interconnected RISC-V MCU. This board serves as a hardware platform for prototyping and developing applications using the CH32V307 microcontroller.

  3. Overview of IoCHub (Internet of Chip Hub)

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    IoCHub is a transparent direct-transmission solution designed to adapt to both Wide Area Networks (WAN) and Local Area Networks (LAN). It allows users to implement efficient, secure, and stable point-to-point data transmission without the need to request fixed IP addresses or domain names. By using a unified set of interfaces, IoCHub facilitates rapid network connectivity and stable data passthrough for MCU interfaces.

  4. Overview of CH32V305/7 RISC-V Microcontrollers

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    The CH32V305/7 series are 32-bit interconnected microcontrollers based on the RISC-V architecture. They are optimized for high-speed interrupt response through a hardware stack area and fast interrupt entry points. The series includes single-precision floating-point instructions (FPU) for enhanced computational performance. Key connectivity features include up to 8 UART/USART interfaces, 4 motor timers, a high-speed USB 2.0 interface (480Mbps) with integrated PHY, and a Gigabit Ethernet MAC with an integrated 10M-PHY module.

  5. Overview of CH32V305 and CH32V307 RISC-V Microcontrollers

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    The CH32V305 and CH32V307 are 32-bit interconnected microcontrollers based on a RISC-V core. They are designed for high performance with features like a hardware stack area and fast interrupt entry, which significantly improves interrupt response speed compared to standard RISC-V implementations.

    Key architectural enhancements include:

    • Single-precision floating point instruction sets and a hardware FPU.
    • Extended peripherals: Up to 8 U(S)ARTs and 4 motor timers.
    • High-speed connectivity: USB 2.0 high-speed interface (480Mbps) with a built-in PHY transceiver, and an upgraded Ethernet MAC supporting GbE with an integrated 10M PHY module.

  7. Understand the structure of the FreeRTOS RISC-V port

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    The FreeRTOS RISC-V port architecture consists of two distinct layers:

    1. Common ISA Code: Located in FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. This file contains the code common to all supported RISC-V chips and is built for all targets.
    2. Chip-Specific Extensions: Provided via freertos_risc_v_chip_specific_extensions.h header files. These files tailor the kernel to specific RISC-V implementations (e.g., handling specific interrupt controllers or register sets).

  8. Understand the structure of FreeRTOS portable layers

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    A FreeRTOS real-time kernel port is composed of two types of files:

    1. Core Kernel Components: Three files that are common to every port.
    2. Specific Files: One or more files tailored to a specific microcontroller and/or compiler.

    To locate the files relevant to your specific hardware and toolchain, follow the directory pattern: FreeRTOS/Source/Portable/[compiler]/[architecture].

  10. Access CH32V307 Datasheets and Manuals

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    The CH32V307 development requires several key documents for hardware specifications, register definitions, and core processor architecture. You can download the following official PDF manuals from the WCH website:

    • Reference Manual (RM): CH32FV2x_V3xRM.PDF - Contains detailed information on peripherals and system configuration.
    • Datasheet (DS): CH32V307DS0.PDF - Provides electrical characteristics, pinouts, and hardware specifications.
    • Core Manual: QingKeV4_Processor_Manual.PDF - Explains the QingKe V4 RISC-V processor architecture.
    Download URLs:
- CH32FV2x_V3xRM.PDF: http://www.wch-ic.com/downloads/CH32FV2x_V3xRM_PDF.html
- CH32V307DS0.PDF: http://www.wch-ic.com/downloads/CH32V307DS0_PDF.html
- QingKeV4_Processor_Manual.PDF: http://www.wch-ic.com/downloads/QingKeV4_Processor_Manual_PDF.html

  11. Use IoCHub AT Commands for MCU functionality

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    The IoCHub_Demo provides a demonstration of point-to-point transmission between MCUs or between an MCU and a system platform. Basic IoCHub functionality on the MCU is controlled via built-in AT commands.

    To interact with the IoCHub via AT commands, use the following serial configuration:

    • Interface: UART1 (PA9/PA10)
    • Baud Rate: 115200
    Interface: UART1 (PA9/PA10)
Baud Rate: 115200

  12. Configure chip-specific extensions for FreeRTOS RISC-V port

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    The FreeRTOS RISC-V port is divided into common ISA implementation code and chip-specific extension code. To ensure the kernel correctly interacts with your specific hardware (such as handling a Core Local Interrupter or specific register extensions), you must include the correct freertos_risc_v_chip_specific_extensions.h header file.

    Crucial Implementation Detail: This inclusion must be performed via the assembler's include path, not the C compiler's include path. Failure to set the assembler path correctly will result in the kernel using incorrect hardware abstractions.

    # Example: If your chip includes a CLINT and no other extensions,
# add this path to your ASSEMBLER include path:
FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions