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ipyxact

repository·main·Indexed 40 days ago

https://github.com/olofk/ipyxact

A Python library for parsing IP-XACT XML files into Python structures. Part of the Lattice Propel Design Environment, it enables programmatic interaction with IP-XACT metadata and includes scripts to generate C header files, Markdown documentation from memory maps, and lists of Verilog files from fileSets.

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What's inside ipyxact

  1. Overview of ipyxact

    main
    ipyxact is a Python-based parser for IP-XACT files. It converts parsed IP-XACT XML files into Python structures, making it easier to programmatically interact with IP-XACT data within Python applications. It is a component of the Lattice Propel Design Environment.

  2. How FIFO Port controls work

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    Each FIFO port in the XYZ ASIC is managed via a triplet of registers: a head register, a tail register, and a status register.

    • Head/Tail: These are 32-bit read-write registers used to manage the data pointers for the FIFO.
    • Status: This register provides real-time feedback on the FIFO state via specific bits:
      • Bit 0: full
      • Bit 1: empty
      • Bit 4: almost_empty
      • Bit 5: almost_full

    Example mapping for Port 0:

    • 0x100: fifo_port_0_head
    • 0x104: fifo_port_0_tail
    • 0x108: fifo_port_0_status

  3. How Virtual Channel (VC) packet counts are structured

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    Virtual Channel (VC) packet counts are tracked in a series of registers starting at address 0x1000. Each register (e.g., vc_pkt_count_0 at 0x1000, vc_pkt_count_1 at 0x1010) follows the same bit layout:

    • vc_count (Bits 30:0): A read-write field representing the number of certain packet types seen.
    • active (Bit 31): A read-write field indicating whether the Virtual Channel is currently active.

    This pattern repeats for each VC (VC 0 through VC 10).

  4. Generate Markdown documentation from memory maps

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    Use the gen_markdown.py script to generate Markdown-formatted documentation for the memory maps contained within an IP-XACT XML file.

    python gen_markdown.py *xml_file*

  7. Reference the XYZ ASIC Register Map

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    The following register map defines the memory-mapped interface for the XYZ ASIC, including chip identification, link status, packet counters, FIFO controls, and Virtual Channel (VC) packet counts.

    Chip Identification and Link Status

    • 0x0 chip_id_reg: Read-only register containing rev_num (bits 3:0) and part_num (bits 31:4).
    • 0x4 link_status: Read-only register showing Serdes Link status for four ports (port0 to port3, each 4 bits wide).

    Packet Counters

    • 0x20 spi4_pkt_count: Read-write register for SPI4 packet counts. port0 is bits 31:16, port1 is bits 15:0.
    • 0x24 gige_pkt_count_reg: Read-write register for GigE packet counts. port0 (31:24), port1 (23:16), port2 (15:8), and port3 (7:0).

    FIFO Port Controls (Ports 0-7)](#fifo-port-controls-ports-0-7)

    Each FIFO port has three associated registers:

    • head: (e.g., 0x100, 0x110, etc.) 32-bit read-write data pointer.
    • tail: (e.g., 0x104, 0x114, etc.) 32-bit read-write data pointer.
    • status: (e.g., 0x108, 0x118, etc.) Read-write status bits:
      • 0: full
      • 1: empty
      • 4: almost_empty
      • 5: almost_full

    Virtual Channel (VC) Packet Counts (VC 0-10)](#virtual-channel-vc-packet-counts-vc-0-10)

    Registers starting at 0x1000 (e.g., vc_pkt_count_0, vc_pkt_count_1, etc.) track packet counts per Virtual Channel:

    • vc_count (bits 30:0): Read-write count of certain packet types.
    • active (bit 31): Read-write flag indicating if the VC is active.
    ## 0x0 chip_id_reg

Bits | Access | Name | Description
-----|--------|------|------------
3:0|read-only|rev_num|This field represents the chips revision number
31:4|read-only|part_num|This field represents the chips part number

## 0x4 link_status

Bits | Access | Name | Description
-----|--------|------|------------
3:0|read-only|port0|Status of a Serdes Link
7:4|read-only|port1|Status of a Serdes Link
11:8|read-only|port2|Status of a Serdes Link
15:12|read-only|port3|Status of a Serdes Link