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OpenTitan Documentation

repository·master·Indexed 25 days ago

https://github.com/lowrisc/opentitan

OpenTitan is an open-source silicon Root of Trust (RoT) project providing transparent and secure hardware and software IP. Managed by lowRISC CIC, the project is organized as a monorepo containing hardware, software, and utilities. Documentation covers environment setup, system and Python dependency installation, simulation tool configuration (Verilator, FPGA, DV), and detailed design signoff checklists for transitions from D0 through V1 stages.

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What's inside OpenTitan

  1. Overview of the Ibex RISC-V Core Wrapper

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    The rv_core_ibex IP template provides a wrapper for the Ibex RV32 CPU core. It integrates the core with TileLink Uncached Light (TL-UL) interfaces for instruction and data ports and supports address translation.

    Key features include:

    • TL-UL Interfaces: Instruction and data ports are exposed via TileLink Uncached Light (TL-UL) host interfaces.
    • Address Translation: Includes simple address translation capabilities.
    • Security & Error Handling: Supports Non-Maskable Interrupts (NMI) for security alert events (e.g., watchdog bark), general error status collection, and alert generation.
    • Debug Support: Provides crash dump collection for software debugging.
    • Configurability: All Ibex configuration parameters are passed through, and the pipelining of the bus adapters is configurable.

  2. Overview of ENTROPY_SRC HWIP

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    The ENTROPY_SRC hardware IP provides an interface to an external physical random noise generator (PTRNG). It collects entropy bits, performs statistical health tests, conditions the data, and stores it in a FIFO for consumption by firmware (via TL-UL bus) or other hardware blocks. It is designed to meet NIST SP 800-90B (full-entropy source) and AIS31 (PTG.2 class) requirements.

    Key Features:

    • Configurable Noise Source: Supports bus widths from 4 to 256 bits.
    • Variable Rate: Maximum rate of one symbol per second clock cycle.
    • Health Testing: Includes Repetition Count, Adaptive Proportion (SP 800-90B), Bucket, Markov, and Mailbox (firmware-defined) tests.
    • Interrupt Support: Triggers for entropy availability, health test failures, and internal FIFO errors.
    • Modes of Operation:
      • FIPS/CC Compliant Mode: Uses SHA-3 conditioning and performs health checks on configurable windows (default 2048 bits).
      • Boot-time / Bypass Mode: Delivers bits faster for on-boot applications by using a smaller 384-bit window and bypassing SHA conditioning.
      • Firmware Conditioning: Allows firmware to manually process raw noise and re-insert it into the pipeline via a TL-UL register.

  3. Overview of I2C HWIP features

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    The I2C hardware IP (HWIP) provides a two-pin bidirectional interface (SCL and SDA) supporting both Controller (Master) and Target (Slave) modes. It is compatible with the I2C specification (rev. 6) and supports speeds up to 1 Mbaud.

    Key Capabilities

    • Supported Modes: Controller and Target.
    • Supported Speeds: Standard-mode (100 kbaud), Fast-mode (400 kbaud), and Fast-mode Plus (1 Mbaud).
    • Controller Features: Start/Stop conditions, ACK/NACK, 7-bit addressing, clock stretching, and bus arbitration/synchronization.
    • Target Features: Automatic clock stretching, programmable automatic ACK control, and responses to broadcast transfers.
    • Interface: Byte-formatted register interface with separate RX and TX queues.
    • Debugging: "Override mode" allows direct SCL and SDA control.
    • Integration: SCL and SDA ports are mapped via the pinmux; the block can be reset using the Reset Manager.

  5. Overview of the OpenTitan Big Number Accelerator (OTBN)

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    The OpenTitan Big Number Accelerator (OTBN) is a specialized coprocessor designed for asymmetric cryptographic operations, such as RSA, Elliptic Curve Cryptography (ECC), and Post-Quantum Cryptography (PQC).

    Key characteristics include:

    • Wide Integer Arithmetic: Features a 256b wide data path with 32 256b wide registers.
    • Control Path: A 32b wide control path with 32 32b wide registers.
    • SIMD Support: Supports both full-width (256-bit) and 32-bit SIMD instructions to efficiently vectorize computations.
    • Security-Focused ISA: Uses a reduced instruction set architecture to minimize data leakage and simplify verification. It intentionally excludes interrupts and exceptions to reduce the attack surface.
    • Memory Model: Operates as a self-contained coprocessor with its own instruction and data memory, accessible as a bus device.
    • Hardware Features: Includes built-in access to random numbers, an interface to offload hashing to KMAC HWIP, and a Masking Accelerator Interface (MAI) for SCA hardened masking operations.

  6. Overview of the Key Manager HWIP

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    The Key Manager Hardware IP (HWIP) implements the hardware component of the OpenTitan identities and root keys strategy. It is designed to shield critical security assets from software while providing a simple model for software to consume derived key and identity outputs.

  7. Overview of the OpenTitan Security Model Specification

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    The OpenTitan Security Model Specification defines the security architecture for discrete silicon implementations. It covers the interaction between device life cycles, secure boot processes, firmware updates, cryptographic identities, attestation, ownership transfer, and provisioning flows. The model is designed to manage device states from manufacturing through to end-user ownership.

  9. Overview of the Pattern Generator (pattgen) HWIP

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    The pattgen (Pattern Generator) is a hardware IP designed to create configurable, time-dependent output patterns. It transmits data on two clock-parallel channels, each consisting of one clock (pcl) and one data (pda) line. The module is controlled via a register interface and can trigger interrupts upon pattern completion. It is designed to follow the OpenTitan Comportability Specification.

  10. Overview of Uvmdvgen

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    uvmdvgen is a Python-based tool used to automate the generation of boilerplate code for UVM agents and complete UVM testbenches. It generates relevant UVM classes, packages, and FuseSoC core files, ensuring compatibility with existing OpenTitan methodologies (DV library or CIP library). This tool is designed to reduce the manual effort and debug cycles typically required when starting a new Design Verification (DV) effort.

  11. Overview of the Platform Integrity Module use case

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    In this use case, an OpenTitan IC acts as a Platform Integrity Module by interposing between a platform's boot flash and its main boot devices (e.g., BMC, PCH, and CPU).

    Key security properties implemented include:

    • Firmware Integrity: Measuring the integrity of first boot firmware stages via SPI (or similar) before releasing boot devices from reset.
    • Device Monitoring: Monitoring resets and heartbeats of downstream boot devices via Interrupt Service Routines (ISRs).
    • Access Control & Updates: Enforcing runtime boot device access policies and managing A/B firmware updates for software in boot flash.
    • Root of Trust: Providing a root key store and attestation flows for secure boot implementation.

  12. Overview of CSRNG HWIP

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    The Cryptographically Secure Random Number Generator (CSRNG) hardware IP provides both deterministic (DRNG) and true random number generation (TRNG) functionalities. It is designed to comply with NIST SP 800-90A/B/C and BSI AIS31 standards.

    Key capabilities include:

    • DRNG Mode: Uses the CTR_DRBG construction (NIST SP 800-90A) with 256-bit security strength, providing Forward Secrecy and Enhanced Backward Secrecy (AIS31 DRG.3).
    • TRNG Mode: When combined with a compliant entropy source, it can function as a non-deterministic random bit generator (NRBG) following the SP 800-90C 'Oversampling Construction' (AIS31 PTG.3).
    • Multi-instance Support: Supports multiple separate CSRNG instances per IP block, each with its own state, control, and reseed counters.
    • Access Control:
      • Instance N-1: Always accessible via the chip interconnect bus through device registers (software access).
      • Other Instances: Typically routed to hardware peripherals (e.g., key manager) and are inaccessible to software during normal operation.
      • Debug Mode: An optional configuration where all instances are accessible to software, which can be permanently disabled via OTP memory for security.