Intel(R) Multi-Buffer Crypto for IPsec Library
repository·main·Indexed 43 days ago
https://github.com/intel/intel-ipsec-mbA high-performance software cryptographic acceleration library optimized for packet processing applications like IPsec and TLS. It provides multi-buffer and burst APIs for encryption (AES-GCM, AES-CCM, Chacha20) and integrity (SHA1, SHA2, SHA3, HMAC) algorithms, leveraging CPU extensions such as SSE, AVX2, AVX512, and AVX10. The library also includes support for Post-Quantum Cryptography (PQC) via ML-DSA (FIPS 204) and ML-KEM (FIPS 203) implementations.
What's inside Intel IPsec-MB
- The Intel Multi-Buffer Crypto for IPsec Library provides highly-optimized software implementations of core cryptographic processing for IPsec, designed to deliver industry-leading performance on Intel(R) Processors. It supports a wide range of encryption, integrity, and post-quantum cryptographic algorithms across various instruction sets (SSE, AVX2, AVX512, AVX10).
Overview of Intel(R) Multi-Buffer Crypto for IPsec Library
mainThe Intel(R) Multi-Buffer Crypto for IPsec Library is a software crypto acceleration library designed primarily for packet processing applications. It is suitable for high-performance use cases such as IPsec, TLS, Wireless (RAN), Cable, or MPEG DRM.
Developers can integrate this library in two ways:
- Via Frameworks: Use it as a software crypto provider within existing frameworks like DPDK, Intel(R) QAT Engine, or FD.io. This allows you to switch crypto providers without modifying your application code.
- Directly: Use the library's native API for direct integration into your application.
Key technical features include:
- Operation Chaining: Combines encryption and authentication operations.
- Advanced Cryptographic Pipelining: Includes a job manager with scheduling and dispatching functions that abstracts implementation details.
- Performance Innovations: Utilizes multi-buffer and function stitching techniques.
- Hardware Optimization: Low-level implementations leverage the latest CPU instruction extensions.
Optimizing Performance via Function Tables or Branches
mainIf your application needs to support both WSM (SSE) and SNB (AVX) architectures to maximize performance, you can use one of two patterns to select the appropriate instruction set functions:
1. Conditional Branching: Use a macro or conditional check to call the specific implementation (e.g.,
submit_job_avxvssubmit_job_sse).#define submit_job(mb_mgr) \ if (_use_avx) submit_job_avx(mb_mgr); \ else submit_job_sse(mb_mgr)2. Function Table: Embed function addresses into a structure and switch the structure pointer at runtime.
struct funcs_t { init_mb_mgr_t init_mb_mgr; get_next_job_t get_next_job; submit_job_t submit_job; get_completed_job_t get_completed_job; flush_job_t flush_job; }; funcs_t funcs_sse = { init_mb_mgr_sse, get_next_job_sse, submit_job_sse, get_completed_job_sse, flush_job_sse }; funcs_t funcs_avx = { init_mb_mgr_avx, get_next_job_avx, submit_job_avx, get_completed_job_avx, flush_job_avx }; funcs_t *funcs = &funcs_sse; if (do_avx) funcs = &funcs_avx; funcs->init_mb_mgr(&mb_mgr);struct funcs_t { init_mb_mgr_t init_mb_mgr; get_next_job_t get_next_job; submit_job_t submit_job; get_completed_job_t get_completed_job; flush_job_t flush_job; }; funcs_t funcs_sse = { init_mb_mgr_sse, get_next_job_sse, submit_job_sse, get_completed_job_sse, flush_job_sse }; funcs_t funcs_avx = { init_mb_mgr_avx, get_next_job_avx, submit_job_avx, get_completed_job_avx, flush_job_avx }; funcs_t *funcs = &funcs_sse; ... if (do_avx) funcs = &funcs_avx; ... funcs->init_mb_mgr(&mb_mgr);Understand the difference between GCM and Multi-Buffer APIs
mainThe library provides two distinct API paths that serve different performance and architectural needs:
GCM API: An optimized single-buffer implementation. It consists of simple computational routines with no associated state. Use this when you need high-performance processing for individual packets or when you want to manage GCM calls independently of your multi-buffer processing logic (e.g., calling them directly in a main thread while enqueuing multi-buffer jobs for a worker thread).
Multi-Buffer API: Designed for high-throughput processing of multiple requests. It uses two parallel interfaces based on processor capabilities:
_ssefunctions: For WSM and later processors._avxfunctions: For processors newer than WSM, offering better performance.
Critical Constraint: You cannot mix these interfaces on the same initialized object. If you initialize an
MB_MGRstructure usinginit_mb_mgr_sse(), you must only use the_ssesuffixed functions with it. If you useinit_mb_mgr_avx(), you must only use the_avxfunctions.Configure AES-CCM chain order
mainWhen using the optimized AES-CCM implementation (introduced in v0.53), the CCM chain order is strictly expected based on the operation type:
- Encryption: Use
HASH_CIPHERorder. - Decryption: Use
CIPHER_HASHorder.
- Encryption: Use
Understand FIPS Compliance and CAVP Support
mainThe Intel(R) Multi-Buffer Crypto for IPsec Library is not a standalone Cryptographic Module (CMVP) certified component, but it is suitable for use as part of a CMVP-certified module.
It supports Cryptographic Algorithm Validation (CAVP) via the
acvp-applocated in thetestdirectory. This application validates a wide range of algorithms including AES (GCM, GMAC, CCM, CBC, ECB, CFB, CTR, CMAC), TDES-CBC, SHA1, SHA2 (224, 256, 384, 512), HMAC-SHA, SHA3, SHAKE, and Post-Quantum algorithms like ML-DSA and ML-KEM.Note: The
acvp-apprequireslibacvp 2.0+to be built.Understand the lib/openssl directory layout
mainThe
lib/openssl/directory mirrors the upstream OpenSSLcrypto/directory layout and contains several specialized algorithm implementations and assembly back-ends:crypto/ml_dsa/: Core ML-DSA (FIPS 204) algorithm (key generation, sign/verify, NTT, matrix/vector arithmetic, sampling, and encoders).crypto/ml_dsa/asm/: Perlasm for ML-DSA NTT/Montgomery arithmetic (AVX2/AVX512), authored by Intel.crypto/ml_kem/: Core ML-KEM (FIPS 203) algorithm (key generation, encapsulation/decapsulation, K-PKE, NTT, and encoders).crypto/sha/: SHA-3/SHAKE single-buffer implementation and its x4 AVX512VL parallel variant.crypto/sha/asm/: Perlasm for the Keccak-1600 permutation (single-buffer and x4 AVX512VL).crypto/perlasm/: OpenSSL's perlasm assembler back-end (x86_64-xlate.pl) and support scripts, used by the assembly implementations above.
Enable Constant-Time Validation for Security Testing
mainThe library supports an optional build mode that uses Valgrind's
memcheckto detect secret-dependent branches and memory accesses. This helps identify potential timing and cache side-channel leaks.How it works
Secrets are marked as "undefined" for Valgrind. If the code branches on or indexes memory using a value derived from these secrets, Memcheck reports an error. This instrumentation propagates from C annotations into hand-written assembly implementations.
Coverage
- ML-DSA/ML-KEM: Full coverage via OpenSSL ML-DSA/ML-KEM sources.
- JOB API AEAD: Covers AES-GCM, SM4-GCM, AES-CCM, ChaCha20-Poly1305.
- JOB API Cipher: Covers AES (CBC, CTR, ECB, CFB), DOCSIS, PON-AES, SM4, ChaCha20, DES, 3DES.
- JOB API Wireless: Covers ZUC, SNOW3G, SNOW5G, KASUMI.
- JOB API Authentication: Covers HMAC (MD5, SHA-1, SHA-2, SHA-3, SM3), AES-GMAC, GHASH, Poly1305, AES-XCBC, AES-CMAC, ZUC, SNOW.
- Unkeyed Digests: Not applicable (e.g., SHA-1, SHA-2, SHA-3, CRC).
Limitations
- Only the JOB API is instrumented. The burst and direct APIs are not currently covered.
- Checks are dynamic and only observe code paths exercised by the test vectors.
- Requires Valgrind development headers and results in significantly slower execution.
Refer to the INSTALL guide for instructions on how to enable this build option.
Supported Processor Architectures and Extensions
mainThe Intel(R) Multi-Buffer Crypto for IPsec Library optimizes performance based on the host processor's instruction set extensions. The library supports several architecture types ranging from SSE to AVX10. Understanding your hardware's capabilities helps in predicting performance characteristics.
Architecture Types Reference
Architecture Type Instruction Extensions Example Products SSE Type 1 SSE4.2, AESNI, PCLMULQDQ, CMOV, BSWAP Westmere, Sandy Bridge, Ivy Bridge, Rangeley, Avoton SSE Type 2 [SSE Type 1] + SHANI Denverton SSE Type 3 [SSE Type 2] + GFNI Snow Ridge AVX2 Type 1 [SSE Type 1] + XSAVE, OSXSAVE, AVX, AVX2, BMI2 Haswell, Broadwell AVX2 Type 2 [AVX2 Type 1] + SHANI, GFNI, VAES, VPCLMULQDQ Arizona Beach, Alder Lake, Raptor Lake AVX2 Type 3 [AVX2 Type 2] + AVX-IFMA Sierra Forest AVX2 Type 4 [AVX2 Type 3] + SM3NI, SM4NI, SHA512NI Lunar Lake AVX512 Type 1 [AVX2 Type 1] + AVX512F, AVX512DQ, AVX512CD, AVX512BW, AVX512VL Sky Lake, Cascade Lake AVX512 Type 2 [AVX512 Type 1] + SHANI, GFNI, AVX512-IFMA, VAES, VPCLMULQDQ Ice Lake, Sapphire Rapids, Emerald Rapids AVX10 Type 1 [AVX512 Type 2] + SM3NI, SM4NI, SHA512NI, APX, AVX10.2 - Post-Quantum Cryptography (PQC) support
mainThe library includes support for post-quantum digital signatures and key-encapsulation mechanisms:
Digital Signatures (ML-DSA)
Supports ML-DSA-44, ML-DSA-65, and ML-DSA-87 (FIPS 204). These are accessed via the opaque
IMB_ML_DSAhandle and theimb_ml_dsa_*API.Key Encapsulation (ML-KEM)
Supports ML-KEM-512, ML-KEM-768, and ML-KEM-1024 (FIPS 203). These are accessed via the opaque
IMB_ML_KEMhandle and theimb_ml_kem_*API.Note: The ML-DSA and ML-KEM implementations are derived from OpenSSL and are licensed under the Apache License 2.0.
Understand the structure of vendored OpenSSL headers
mainThe
lib/include/openssl/directory contains two distinct types of headers used to support the vendored OpenSSL sources inlib/openssl/.- Genuine OpenSSL Headers: Located in
crypto/andinternal/, these are ported directly from upstream OpenSSL (specifically from commit626ff8fd9344eb46e50464960ce84dcbacf5a4dd). They mirror the upstreaminclude/crypto/andinclude/internal/trees and are licensed under the Apache License 2.0. - Compatibility Shims: Located in
compat/, these provide the OpenSSL-compatibility surface required by the vendored ML-DSA and ML-KEM code. These shims bridge the gap between the ipsec-mb primitives and the expected OpenSSL API.
- Genuine OpenSSL Headers: Located in
How the Intel IPsec MB asynchronous job model works
mainThe library operates on an asynchronous paradigm where the application submits 'jobs' to a Multi-Buffer Manager (
MB_MGR) and retrieves them once processing is complete.Core Workflow:
- Acquire: Call
get_next_job()to get a pointer to a newJOB_AES_HMACstructure. The library manages the lifecycle of these objects; data in a job is guaranteed to be valid until the next call toget_next_job(). - Configure: Fill in the fields of the
JOB_AES_HMACstructure (see Job Fields). - Submit: Call
submit_job()to send the job to the manager. This returns a pointer to the job if it was completed immediately, orNULLif it is still outstanding. - Retrieve Completed Jobs: Use
get_completed_job()to poll for completed jobs. This helps reduce latency and manage the number of outstanding jobs. - Flush: If there is a lull in incoming work, call
flush_job()to force the completion of the earliest outstanding job. This prevents jobs from sitting in the manager with high latency during idle periods.
init_mb_mgr(&mb_mgr); // ... key expansion ... while (work_to_be_done) { job = get_next_job(&mb_mgr); // TODO: Fill in job fields job = submit_job(&mb_mgr); while (job) { // TODO: Complete processing on job job = get_completed_job(&mb_mgr); } }- Acquire: Call