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SkyWater Open Source PDK

repository·main·Indexed 25 days ago

https://github.com/google/skywater-pdk

A complete open-source process design kit for the SKY130 130nm technology node. It enables the creation of manufacturable ASIC designs using open-source EDA tools such as Magic, ngspice, OpenRoad, and Yosys, as well as commercial tools like Cadence Virtuoso and Mentor Calibre. The PDK includes detailed specifications for standard cell libraries (high speed, medium speed, low power, high density, and high voltage), library naming conventions, capacitor types (MiM and MoM), and essential design verification terms like DRC, LVS, and PEX.

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What's inside skywater-pdk

  1. Overview of SkyWater Open Source PDK

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    The SkyWater Open Source PDK is a collaboration between Google and SkyWater Technology Foundry. It provides a fully open-source Process Design Kit (PDK) and related resources for creating manufacturable designs at SkyWater's facility.

    Currently, the repository targets the SKY130 process node (a 180nm-130nm hybrid technology).

    Important Note: The current content is an experimental preview / alpha release. It is intended for test chips and initial design verification, but is not currently intended for production settings. Production versions will be tagged when ready.

  2. Overview of the SkyWater Open Source PDK

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    The SkyWater Open Source PDK is a collaboration between Google and SkyWater Technology Foundry. It provides a fully open-source Process Design Kit (PDK) and related resources for creating manufacturable designs at SkyWater's facility. The repository currently targets the SKY130 process node.

  4. Understand the current status of the SkyWater PDK

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    The SkyWater Open Source PDK is currently in an experimental preview / alpha release stage.

    Usage Guidelines:

    • Not for Production: The PDK is not intended for production settings at this time.
    • Recommended Use: It is suitable for test chips and initial design verification, though use for these purposes is not guaranteed.
    • Production Readiness: A production version will be released and tagged once it is ready for production design. Refer to the Versioning Information section in the documentation for details on the version numbering scheme.

    To receive notifications regarding new releases and important updates, subscribe to the skywater-pdk-announce mailing list.

  5. Choose simulation models for SKY130

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    The SkyWater SKY130 PDK provides two types of simulation models depending on your toolchain:

    1. Spectre models: Designed for use with Cadence Spectre.
    2. Spice models: Compatible with popular open-source spice simulators, such as ngspice.

  6. Identify Very High Voltage (VHV) Devices

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    Very High Voltage (VHV) is defined as any voltage outside the range of GND to High Voltage (11V).

    • VHV Threshold: Voltages exceeding 11V (e.g., 16V or 12V nominal Vcc).
    • Device Classification: Any device subjected to a voltage outside the GND to 11V range is considered a Very High Voltage (VHV) device and must follow specific VHV implementation methodologies and design rules.

  7. Download and update the SkyWater Open Source PDK

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    To download or update to the 'latest' version of all standard cell libraries and regenerate the liberty files, clone the repository and execute the following commands. Note that the download is large (approximately 7GB).

    # Expect a large download! ~7GB at time of writing.
SUBMODULE_VERSION=latest make submodules -j3 || make submodules -j1

# Regenerate liberty files
make timing

  8. Understand Antenna Rules and EGAR calculation

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    Antenna rules limit the ratio of interconnect area exposed to plasma etch relative to the active gate poly area electrically connected to it. To pass verification, the calculated Etch Gate Area Ratio (EGAR) must satisfy the condition:

    EGAR <= MAX_EGAR

    Calculation Formulas

    When a diode is used: EGAR = (EA / A_gate) - K * (AntennaDiode_area in um2) - diode_bonus

    When diodes are not used: EGAR = (EA / A_gate)

    Variables:

    • EA: Interconnect area exposed to plasma etch.
    • A_gate: Active gate poly area.
    • K: A multiplying factor specified for each layer.
    • AntennaDiode_area: The area of the AntennaDiode used to discharge the interconnect area (set to 0 if no diode is used).
    • diode_bonus: A unitless value applied when at least one diode is used, regardless of its size.

  9. Handle Un-shielded VPP routing capacitance

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    Any routing placed above an un-shielded VPP will not be extracted during RCX.

    Impacts:

    • Total capacitance and parasitic capacitance impacts are already included in the model corners.
    • Cross-talk is not modeled.
    • Parasitic capacitance is routed to ground, which may not be ideal for all scenarios.
    • Estimation: You can estimate the parasitic capacitance using RescapWeb.

  10. Use Bipolar NPN transistors in SKY130

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    The SKY130 process provides NPN devices that use the deep n-well as the collector. These devices are not optimized and must be used in forward-active mode. Reverse-active mode operation is neither modeled nor permitted.

    Implementation Requirements

    • Guard Rings: You must use the device in conjunction with the correct guard rings to prevent latchup issues with nearby circuitry.
    • Poly-gated version: The sky130_fd_pr__npn_11v0 model includes a poly gate between the emitter and base diffusions to prevent carrier recombination at the STI edge and increase $\beta$. This poly gate must be connected to the emitter terminal to prevent the parasitic MOSFET from turning on.

    Available Device Sizes

    • Ungated device with emitter 1.0 x 1.0
    • Ungated device with emitter 1.0 x 2.0
    • Poly-gated version with octagonal emitter of $A = 1.97 \mu m^2$

  11. Understand Parasitic Layout Extraction (RCX) limitations

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    When performing Parasitic Layout Extraction (RCX) using Assura, be aware of the following modeling and extraction limitations in the SKY130 process:

    • M1/M2 Capacitance: Models include M1/M2 capacitance. However, due to RCX extraction limitations, M1/M2 routing over a varactor will have no capacitance extraction.
    • Precision Resistors (xhrpoly_X_X): Avoid routing or placing devices over or under precision resistors. The parasitic capacitance between precision resistors and any routing/devices is not included in layout RCX.
    • MIMC (3-terminal MIMC): Parasitic capacitance between 3-terminal MIMC and any routing/devices is not included in layout RCX, with the exception of M3 (up to 1 snap grid width).
    • MIMC Fringing: No artificial fringing capacitance is extracted for MIMC M2/M3 due to the CAD algorithm after CAPM sizing.
    • RF ESD Diodes: S8Q-5R is not supported for RF ESD diode RCX blocking.
    • Substrate Cut: The areaid:substratecut will be extracted as a 0.123 ohm two-term resistor.