Understand the Compiler Backend Design
masterThe Mezzano compiler backend processes optimized ASTs into Intermediate Representation (IR) instructions, which are then converted to assembly.
Key design concepts:
- Instruction Structure: Instructions are linked via an intrusive doubly-linked list. Basic blocks are implicit, started by a
labelinstruction and ended by aterminator-instruction. - Function Entry: The first instruction in any function must be an
argument-setup-instruction. - Data Flow: Uses
virtual-register(vreg) objects. In SSA form, a vreg is defined exactly once. Physical registers (preg) can be used directly, but they cannot be live over basic block boundaries until after register allocation. - Lexical Variables: Represented by the
lexical-variableclass. They are explicitly bound and unbound and are not converted to SSA form to preserve debug lifetime information. - Multiple Values: Handled outside the vreg/preg system using target-specific multiple value registers. They can only be live over a small set of instructions.