Espressif ESP-IDF Documentation

repository·master·Indexed 29 days ago

https://github.com/espressif/esp-idf

Documentation for the Espressif IoT Development Framework (ESP-IDF). Includes details on ESP-TEE security framework, BLE Log module APIs, ESP-BLE-MESH networking, and component testing for various Espressif SoCs including ESP32, ESP32-C series, ESP32-S series, and ESP32-H series.

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What's inside espressif-esp-idf

  1. Overview of Unified Provisioning in ESP-IDF

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    Unified Provisioning provides an extensible mechanism for configuring device Wi-Fi credentials and other custom settings using different transport methods and security schemes. It is designed to be flexible, allowing developers to send custom configuration data and use various data formats.

    Key features include:

    • Extensible Protocols: Supports custom configuration data and custom data formats.
    • Flexible Transport: Works over Wi-Fi (SoftAP + HTTP server) or Bluetooth Low Energy (BLE) via GATT.
    • Flexible Security: Supports various security levels, from no encryption to application-layer security using Proof-of-Possession (PoP).
    • Compact Data Format: Uses Google Protobufs for session setup and network provisioning, though developers can choose other formats.
  2. Overview of ESP-BLE-AUDIO profiles and services

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    ESP-BLE-AUDIO implements the Bluetooth LE Audio architecture using the LC3 codec and LE Isochronous Channels (CIS/BIS). The API is organized into a generic audio framework and use-case specific profiles.

    Generic Audio Framework

    • Common Audio Profile (CAP) & Common Audio Service (CAS): Coordinates audio procedures across single or multiple devices.
    • Basic Audio Profile (BAP): Handles unicast/broadcast stream setup, codec configuration, and stream control.
    • Published Audio Capabilities (PACS): Advertising and negotiating audio capabilities.
    • Audio Stream Control Service (ASCS): Exposes sink/source audio endpoints on a BAP Unicast Server.
    • Broadcast Audio Scan Service (BASS): Offloads BIS scanning from a low-power Scan Delegator.
    • Volume Control Profile (VCP): Includes Volume Control Service (VCS), Volume Offset Control Service (VOCS), and Audio Input Control Service (AICS).
    • Microphone Control Profile (MICP): Manages microphone mute and gain.
    • Coordinated Set Identification Profile (CSIP): Identifies set members (e.g., left/right earbuds).
    • Media Control Profile (MCP) & Service (MCS): Provides media control functionality.
    • Call Control Profile (CCP) & Telephone Bearer Service (TBS): Manages telephony and in-call control.

    Use Case Specific Profiles

    • Hearing Access Profile (HAP): Hearing aid presets and control.
    • Gaming Audio Profile (GMAP): Specialized audio for gaming (Gateways/Terminals/Senders/Receivers).
    • Telephony and Media Audio Profile (TMAP): Interoperability for telephony and media use cases.
    • Public Broadcast Profile (PBP): Discovery and subscription to public broadcast streams.
  3. Overview of ESP Hardware Abstraction Layer for System Timer (esp_hal_systimer)

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    The esp_hal_systimer component provides a unified interface for interacting with the System Timer (SYSTIMER) peripheral across all ESP chip families. It abstracts hardware-specific details to allow consistent usage patterns for high-resolution timing operations.

    Key uses for the SYSTIMER include:

    • System time tracking
    • FreeRTOS tick generation
    • High-precision timing operations
    • Event Timer Module (ETM) trigger generation
    WARNING

    This component is currently in beta. Its API, behavior, and compatibility may change without notice, and backward compatibility is not guaranteed.

  4. Overview of Flash Encryption

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    Flash encryption protects the contents of the external flash chip used by the SoC. When enabled, firmware is initially flashed in plaintext, and the data is encrypted during the first boot. This prevents physical reading of the flash from recovering most of the firmware content.

    Key Considerations:

    • Production Use: Flash encryption should only be enabled in mass production mode.
    • Updates: Enabling flash encryption will restrict subsequent firmware updates. Review the implications before enabling.
    • Secure Boot: Secure Boot is a separate feature that can be used alongside flash encryption to create a more secure environment.
  5. Overview of ESP Hardware Abstraction Layer for Parallel IO (esp_hal_parlio)

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    The esp_hal_parlio component provides a Hardware Abstraction Layer (HAL) for Parallel IO (PARLIO) peripherals. It enables high-speed parallel data transfer between an ESP chip and external devices, supporting both transmit (TX) and receive (RX) operations.

    Note: This component is currently in beta. Its API, behavior, and compatibility may change without notice, and backward compatibility is not guaranteed.

  6. Overview of BluFi for Wi-Fi Provisioning

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    BluFi is a Wi-Fi network configuration function that uses a Bluetooth channel to securely pass Wi-Fi credentials (like SSID and password) to an ESP32 device. It supports fragmenting, data encryption, and checksum verification.

    Important Note: BluFi is currently in maintenance mode. For new projects or when adding Wi-Fi provisioning, it is highly recommended to use the network_provisioning component instead, as it is a modern, secure, and actively maintained solution.

  7. Overview of ESP Hardware Abstraction Layer for Analog Comparator

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    The esp_hal_ana_cmpr component provides a Hardware Abstraction Layer (HAL) for Analog Comparator peripherals. It allows developers to compare two analog voltage signals to generate digital outputs, which is useful for threshold detection, zero-crossing detection, and analog signal monitoring.

    Note: This component is currently in beta. The API, behavior, and compatibility may change without notice, and backward compatibility is not guaranteed.

  8. Overview of the Wear Levelling component

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    The Wear Levelling component helps extend the life of SPI flash by distributing erase and write operations evenly across all sectors, preventing specific sectors from being overused.

    It provides low-level APIs for reading, writing, erasing, and memory mapping external SPI flash. It also provides higher-level APIs designed to work in conjunction with the FAT file system.

    Operating Modes

    The component supports different sector sizes and operational modes to balance performance and data safety:

    1. Standard Mode (FAT Integration): Uses 4096-byte sectors (standard flash sector size). This offers the best performance but consumes more RAM.
    2. Performance Mode (512-byte sectors): Data is first stored in RAM, the sector is erased, and then data is written back to flash. Warning: If power is lost during the erase/write cycle, the entire 4096-byte sector's data will be lost.
    3. Safe Mode (512-byte sectors): Data is first stored in an empty flash sector, the target sector is erased, and then data is moved back. This mode allows for immediate data recovery if power is lost.

    Default Settings:

    • Sector size: 512 bytes
    • Mode: Performance mode

    Settings can be modified via the configuration menu (Kconfig).

  9. Overview of the SPI Master Driver

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    The SPI Master driver controls the General Purpose SPI (GP-SPI) peripherals of the SoC when it acts as a master (Host). It manages communication between a Host (the SPI controller) and one or more Devices (SPI slaves) connected to a shared Bus.

    Key Terminology

    • Host: The SPI controller peripheral that initiates transmissions.
    • Device: The SPI slave. Each device has a unique CS (Chip Select) line.
    • Bus: The shared signal lines (MISO, MOSI, SCLK, and optionally QUADWP/QUADHD) used by all devices on a host.
    • Transaction: An atomic sequence of asserting a CS line, transferring data, and de-asserting the CS line.

    Driver Features

    • Supports multi-threaded environments.
    • Transparently handles DMA transfers for reading and writing.
    • Provides automatic time-division multiplexing for multiple devices on the same bus.
  10. Overview of TinyCrypt Cryptographic Library

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    TinyCrypt is a lightweight cryptographic library designed for constrained devices. It provides a minimal set of standard primitives with a focus on minimizing code size and dependencies.

    Supported Primitives:

    • Hashing: SHA-256
    • MAC: HMAC-SHA256, AES-CMAC
    • PRNG: HMAC-PRNG (256-bit), CTR-PRNG (128-bit)
    • Block Cipher: AES-128
    • AES Modes: CBC, CTR, CMAC, CCM (Authenticated Encryption)
    • Elliptic Curve (NIST p-256): ECC-DH (Key Exchange), ECC-DSA (Digital Signature)

    Design Goals:

    • Minimize code size for each primitive.
    • Minimize dependencies so only required primitives are compiled and allocated.
  11. Overview of ESP Hardware Abstraction Layer for PPA Peripheral

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    The esp_hal_ppa component provides a Hardware Abstraction Layer (HAL) for the PPA (Pixel Processing Accelerator) peripheral. It is designed to support various ESP-IDF targets that implement PPA hardware.

    Note: This component is currently in beta. Its API, behavior, and compatibility may change without notice, and backward compatibility is not guaranteed. Use with caution in production systems.

  12. Overview of ESP Hardware Abstraction Layer for PMU and RTC Control

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    The esp_hal_pmu component provides a Hardware Abstraction Layer (HAL) for the Power Management Unit (PMU), legacy RTC Control (RTC_CNTL), and Power Assist Unit (PAU) peripherals. It enables unified power management operations across different ESP chip families, including sleep mode control, power domain management, wakeup configuration, and retention control.

    Note: This component is currently in beta. Its API, behavior, and compatibility may change without notice, and backward compatibility is not guaranteed. Use with caution in production systems.