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LiteEth Ethernet Core

repository·master·Indexed 43 days ago

https://github.com/enjoy-digital/liteeth

A small-footprint, highly configurable Ethernet core for FPGAs built using Migen and part of the LiteX ecosystem. It supports various PHY interfaces including MII, RMII, GMII, RGMII, SGMII, 1000BaseX, and 2500BaseX, with protocol support for ARP, ICMP, UDP, and DHCP. Features include Etherbone (Wishbone over UDP) and UDP streaming, with specific integration guides for the Gowin GW5 1000BASE-X PHY and Sipeed Tang Mega 138K Pro.

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What's inside LiteEth

  1. LiteEth core features and PHY support

    master

    LiteEth is a configurable Ethernet core powered by Migen. It supports various PHY interfaces and protocol implementations.

    Supported PHY Interfaces

    • 100Mbps: MII, RMII
    • 1Gbps: GMII, RGMII, SGMII, 1000BaseX
    • 3.125Gbps: SGMII, 2500BaseX

    Core Capabilities

    • MAC: Configurable with either Hardware or Software interfaces.
    • Protocols: Support for ARP, ICMP, UDP (HW or SW), and DHCP.
    • Frontend:
      • Etherbone: Wishbone over UDP (supports both Slave and Master modes).
      • UDP Streaming.

  2. Getting started with LiteEth

    master

    To use LiteEth, you need to set up a Python environment and the LiteX ecosystem. LiteEth can be used as a LiteX library or integrated into standard design flows by generating Verilog RTL.

    Prerequisites

    1. Install Python 3.6+.
    2. Install your specific FPGA vendor's development tools.
    3. Install LiteX and its associated cores by following the LiteX installation guide.

    Integration

    • LiteX Integration: Examples of how to integrate the core with LiteX can be found in the LiteX-Boards repository or within the examples/ directory of this repository.
    • Standard Design Flow: You can generate Verilog RTL from the Migen description to use LiteEth as a standard core in other tools.

  3. Modify SerDes configuration for GW5 1000BASE-X

    master

    The SerDes initialization is managed via embedded TOML and register writes. If you need to change the SerDes configuration (e.g., switching lanes), you must export the embedded TOML and use the Gowin serdes_toml_to_csr generator to create a new .csr file.

    Regenerating for Lane 1

    To generate a configuration for lane 1 (where lane 0 is the other_lane):

    1. Export the TOML template from the Python module.
    2. Run the Gowin generator tool against the generated TOML.

    Regenerating for Lane 0

    Use lane=0 and other_lane=1 in the template.

    Note: After regenerating, you must update the corresponding _serdes_csr[lane] entry in the source and update vendor-configuration checksums in the tests.

    # 1. Export TOML for lane 1
python3 -c 'from liteeth.phy.gw5_1000basex import _serdes_toml; print(_serdes_toml.format(lane=1, other_lane=0), end="")' > gw5_1000basex.toml

# 2. Run Gowin generator to create the CSR file
/path/to/gowin/IDE/bin/serdes_toml_to_csr.dist/serdes_toml_to_csr_138k.bin \
    gw5_1000basex.toml -o gw5_1000basex.csr --comment

  4. Run LiteEth unit tests

    master

    LiteEth includes unit tests located in the ./test/ directory. You can run the full test suite using the setup script or run specific tests using the Python unittest module.

    # Run all unit tests
$ ./setup.py test

# Run a specific test individually
$ python3 -m unittest test.test_name

  5. Setup Tang Mega 138K Pro with 1000BASE-X

    master

    To use the 1000BASE-X PHY on a Sipeed Tang Mega 138K Pro, ensure you have the LiteX-Boards target support and the LiteX Gowin false-path constraint fix installed.

    Build and Load Command

    Use the following command to build and load the target. You can specify the SFP port using --eth-sfp:

    • --eth-sfp=0: Uses SFP-0 (Default).
    • --eth-sfp=1: Uses SFP-1.

    Hardware Configuration

    • Connect the selected SFP to a 1000BASE-X peer.
    • Retain the dock's 100 MHz PLL0 reference-clock setting.
    • The target maintains its default DDR3 and Etherbone buffer configurations.
    # Default (SFP-0)
python3 -m litex_boards.targets.sipeed_tang_mega_138k_pro \
    --with-etherbone --eth-phy=1000basex --eth-ip=192.168.1.50 --build --load

# Using SFP-1
python3 -m litex_boards.targets.sipeed_tang_mega_138k_pro \
    --with-etherbone --eth-phy=1000basex --eth-ip=192.168.1.50 --eth-sfp=1 --build --load

# Verify connection
ping 192.168.1.50

  6. Use the Gowin GW5 1000BASE-X PHY

    master

    The GW5_1000BASEX module connects LiteEth's 8b/10b PCS and autonegotiation to a GTR12_QUAD SerDes via a raw 10-bit interface at 125 MHz.

    It is designed for the GW5AST-138B platform, specifically targeting Q1 lane 0 or 1 with a 100 MHz differential reference on Q1 REFCLK1. On the Tang Mega 138K Pro dock, these correspond to the SFP-0 and SFP-1 connections.

    Key Features

    • Lane Selection: Use GW5_1000BASEX(platform, lane=0) for SFP-0 or lane=1 for SFP-1. Lane 0 is the default.
    • PHY Control:
      • ethphy_reset: Resets the lane and PCS.
      • ethphy_status: Reports status in bits 0–3:
        • Bit 0: Transmit PLL lock
        • Bit 1: Receive CDR lock
        • Bit 2: Comma alignment
        • Bit 3: PCS link-up
    • Hardware Requirements: The board target must enable the SFP transmitter and provide the reference clock. Note that the SerDes cannot be shared with PCIe simultaneously; the board target rejects simultaneous 1000BASE-X and PCIe use.
    # Example instantiation logic (conceptual)
# lane=0 is default (SFP-0)
phy = GW5_1000BASEX(platform, lane=0)

# lane=1 for SFP-1
phy = GW5_1000BASEX(platform, lane=1)