LiteDRAM Documentation

The RPC DRAM PHY supports Reduced Pin Count (RPC) DRAM from Etron, which provides DDR3/DDR3L-level bandwidth using only 22 or 24 pins.

Pinout

• CLK/CLK#: Differential clock
• CS#: Chip select
• DQS/DQS#: Differential data strobe (optional DQS0/DQS0#)
• DB[15:0]: Parallel commands and DDR data
• STB: Single serial line for serial commands (held low before each transaction)

Command Mechanism

Unlike standard DDR3, RPC does not use dedicated command/address lines. Instead, commands are encoded on the DB and STB lines. The protocol uses a hybrid approach:

1. Parallel Commands: The first command in a sequence is sent via the DB lines.
2. Serial Commands: Subsequent commands in a sequence are transmitted as serial commands via the STB line.

The LPDDR4 PHY in LiteDRAM is designed with a vendor-agnostic core that operates in the memory controller's clock domain. This core is then extended by specific hardware wrappers (e.g., for Xilinx Series 7 FPGAs).

Key architectural components include:

• Core (LPDDR4PHY): Handles DFI command translation and manages 8 DFI phases (due to LPDDR4's 16n prefetch). It includes BitSlip modules and CSRs for read/write bitslip control.
• Command Translation: Uses DFIPhaseAdapter and Command modules to map DFI commands to LPDDR4 CS/CA sequences. Because LPDDR4 commands often require subcommands (e.g., READ-1 + CAS-2), commands may span multiple clock cycles.
• Wrappers: Concrete implementations (like S7LPDDR4PHY) derive from the base PHY to handle signal serialization/deserialization using hardware primitives like IOSERDESE2 and IODELAYE2.

When implementing a new concrete PHY, you can use the existing simulation PHYs in lpddr4/simphy.py as a reference.

• LPDDR4SimPHY: Wraps the core and performs serialization using Migen serializers.
• DoubleRateLPDDR4SimPHY: A double-rate version of the simulation PHY.

These classes are used directly for Migen unit tests, which verify sequences of commands on the DFI against expected sequences on the pads.

Standard LPDDR4 uses 8 DFI phases, which would require 16:1 serialization for DDR signals like DQ. Since many FPGA primitives (like Xilinx Series 7 OSERDESE2) only support up to 14:1 serialization, you should use DoubleRateLPDDR4PHY.

DoubleRateLPDDR4PHY is a wrapper over LPDDR4PHY that performs partial (de-)serialization. This effectively halves the widths of all signals, allowing the use of 8:1 serializers instead of 16:1.

To use LiteDRAM, you must first set up the Python environment and the LiteX ecosystem. LiteDRAM is designed to be used as a LiteX library or integrated into standard design flows by generating Verilog RTL.

Prerequisites

• Python 3.6 or higher
• Your specific FPGA vendor's development tools (e.g., Xilinx Vivado, Altera Quartus, etc.)

Installation Steps

1. Install Python 3.6+ and your FPGA vendor's development tools.
2. Install LiteX and the associated cores by following the official LiteX installation guide.

When using RPC DRAM on a modified Arty A7 board, the DRAM requires 1.5V instead of the standard 1.35V. To support this, the onboard Power Management IC (PMIC) must be reconfigured via I2C during board startup. This requires connecting I2C pins to the J11 pads near the DC jack and user LEDs.

#include <i2c.h>
unsigned char vbuck2_15 = 0x78;
i2c_write(0x58, 0xa3, &vbuck2_15, sizeof(vbuck2_15));  // Vbuck2A
i2c_write(0x58, 0xb4, &vbuck2_15, sizeof(vbuck2_15));  // Vbuck2B

LiteDRAM includes unit tests located in the ./test/ directory. You can run the full suite using the provided setup script or run specific tests using the Python unittest module.

# Run all unit tests
$ ./setup.py test

# Run a specific test individually
$ python3 -m unittest test.test_name

When creating a concrete implementation of an LPDDR4 PHY, you should derive from LPDDR4PHY (defined in basephy.py).

Key Requirements:

• Signal Grouping: The core converts self.dfi signals into self.out of type LPDDR4Output. Your wrapper must (de-)serialize these signals.
• Latency Management: Because concrete wrappers add latency, you must provide ser_latency (serialization latency) and des_latency (deserialization latency) parameters to the wrapper. These are used by the core to calculate PhySettings correctly.
• BitSlip: The core LPDDR4PHY provides BitSlip modules and CSRs for read/write bitslip control, but any specific DQ/DQS delays must be implemented within your concrete PHY implementation.

For Xilinx Series 7 FPGAs, use S7LPDDR4PHY. This implementation wraps DoubleRateLPDDR4PHY and utilizes specific hardware primitives:

• IOSERDESE2 for serialization/deserialization.
• IODELAYE2 for signal delays.

Variants for different Series 7 families are available, following the same pattern as S7DDRPHY.