ch32fun Development Environment

The spi_oled example provides a complete graphics stack for SSD1306 displays using the CH32V003 SPI peripheral:

• Low-level Interface: Provides generic SPI port initialization and a write-only transmit interface.
• High-level Graphics Driver: Supports drawing:
  • Pixels
  • Lines
  • Circles
  • Rectangles
  • 8x8 character font rendering

Supported display dimensions: 64x32, 128x32, and 128x64.

ch32fun is an open-source development environment (tooling, headers, and examples) for WCH RISC-V chips, specifically optimized for the CH32V003. Unlike standard HALs (Hardware Abstraction Layers) which can be heavy and complex, ch32fun aims to provide a lightweight environment that allows developers to interact directly with the hardware as described in the Technical Reference Manual (TRM).

Key components include:

• minichlink: A cross-platform tool for flashing and debugging using various programmers (WCH Link-E, ESP32S2, Arduino-based, etc.).
• ch32fun headers/source: A self-contained set of files for compiling applications.
• Debug Support: High-speed printf over the single-wire programming interface (~36kB/s) and GDB server support for VSCode/Visual Studio.

The usbfs_device example demonstrates basic USB Full Speed (USBFS) functionality by creating two HID (Human Interface Device) devices:

1. Keyboard: Simulates sending 3 presses of the 8 key.
2. Mouse: Simulates moving the cursor diagonally towards the bottom right corner of the screen.

You can verify HIDAPI transfers using the testtop program located in the corresponding subdirectory.

This example demonstrates Gigabit Ethernet functionality using the CH32V307 (QFN68 package) paired with the RTL8211E-VB-CG PHY.

Behavior:

• Automatically negotiates network speed.
• Prints any broadcast packets detected to the debug interface.
• Periodically sends a custom broadcast packet with an incrementing byte, which can be monitored using Wireshark.

iSLER provides RX/TX capabilities for WCH RF-enabled microcontrollers within the ch32fun ecosystem. It supports 1M and 2M PHYs across all listed chips, with S2 and S8 Coded PHY support currently available on specific models.

Supported MCU Capabilities

Note: Support for ch571/3 is experimental. TX is currently non-functional, and RX status is uncertain due to manual DMA handling requirements.

Hardware Recommendations

For full feature support, including Long Range Coded PHY (S2/S8), the ch582 is recommended as the most cost-effective option.

The branchless_gpio_lib is an Arduino-like library designed for high performance and minimal code size. It provides abstractions for:

• Digital I/O: Reading and writing digital pins.
• Analog-to-Digital (ADC): Reading analog voltages.
• Digital-to-Analog (PWM): Generating PWM signals.

The library is optimized to be extremely lightweight; for example, a blink example using this library compiles to only 504 bytes.

The USBHS (USB High Speed) peripheral is available on the following chip families:

• CH32V205
• CH32V305
• CH32V307
• CH32V317
• CH32X305
• CH32X315
• CH32H415
• CH32H416
• CH32H417
• CH565
• CH569
• CH584
• CH585

To use C++ classes with virtual methods in ch32fun, you must ensure that the virtual table (vtable) is correctly initialized during startup. This is achieved by providing an implementation of __libc_init_array.

In ch32fun, you enable this behavior by defining the CPLUSPLUS macro. Without this macro, the vtable will not be initialized, leading to invalid calls (often resulting in MCU resets or hard faults) when attempting to invoke virtual methods.

When configuring LoRa communication, adjust the following main parameters to balance range, data rate, and airtime:

• SF (Spreading Factor): Controls range vs. airtime. Larger SF (e.g., SF11) increases range but increases time on air. SX126X supports SF5 through SF11.
• BW (Bandwidth): Higher bandwidth allows for higher data rates but reduces sensitivity.
• CR (Coding Rate): Higher coding rates provide better error correction and range at the cost of data rate and airtime.

Compatibility Note: While SX126X and SX127X can generally communicate, SF6 on an SX126X is not backward compatible with SF6 on an SX127X.

The inductance tester achieves high precision by using the DMA (Direct Memory Access) subsystem and a timer to perform IO operations while the main CPU is asleep. This allows for cycle-accurate operations that are difficult to achieve with the CPU alone.

The process is driven by three data tables:

1. values: The specific values the peripherals will be set to.
2. addresses: The memory addresses of the peripherals being targeted.
3. times: The number of clock cycles to wait between each operation.

Constraints:

• The DMA can perform only one operation at a time.
• There is a minimum required time between operations of approximately 15 clock cycles.

The implementation of the inductance tester differs slightly depending on the chip used to optimize timing and bus usage:

• CH32V003: The code waits for the input to become free. This is efficient because the loop is tight enough to fit in the cache.
• CH32V006: The code performs a wfi (Wait For Interrupt) to put the CPU to sleep. This ensures the CPU does not use the bus while the DMA is performing its timed operations, improving precision.