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Chisel Hardware Description Language

repository·main·Indexed 26 days ago

https://github.com/chipsalliance/chisel

An open-source hardware description language (HDL) embedded in Scala used to create parameterizable and reusable hardware generators. Chisel compiles into synthesizable Verilog via the FIRRTL/CIRCT framework. The project includes a Scalac compiler plugin for Bundle optimizations, a standard library for circuit generators, and support for simulation-based verification using svsim and chiseltest.

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What's inside Chisel

  1. Overview of Chisel testing strategies

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    Chisel supports multiple testing strategies depending on the verification goal:

    1. Simulation: The primary strategy using ChiselSim, which simulates Chisel-generated SystemVerilog using various simulators.
    2. Text Inspection: A complementary strategy used to directly inspect the generated SystemVerilog or FIRRTL text, typically using FileCheck.

    It is recommended to use a mix of these strategies to achieve comprehensive verification.

  2. Overview of svsim

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    svsim is a low-level library designed for compiling and controlling SystemVerilog simulations. It is not a testing framework itself, but rather a foundational layer that provides backend-independent test harnesses. It is intended to be used by higher-level testing frameworks to enable SystemVerilog simulation.

    Key characteristics:

    • Backend-independent: Generated test harnesses and simulation control logic work across different backends (currently targeting Verilator and VCS).
    • Low-level API: Provides explicit control without syntactic sugar, allowing higher-level frameworks to implement their own peek/poke or Data abstractions.
    • Pipelined Communication: Uses an ad-hoc protocol via stdin and stdout that allows the Scala driver to send multiple commands before processing responses, minimizing communication overhead.

  3. Overview of Chisel

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    Chisel (Constructing Hardware in a Scala Embedded Language) is an open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level. It adds hardware construction primitives to the Scala programming language, allowing designers to write complex, parameterizable circuit generators that produce synthesizable Verilog. Chisel is powered by FIRRTL (Flexible Intermediate Representation for RTL), a hardware compiler framework implemented by LLVM CIRCT.

  4. Understand Chisel Terminology for Hardware Connections

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    To use connection operators effectively, understand these core Chisel concepts:

    • Chisel type: A Data object not bound to hardware (e.g., UInt(3.W), new Bundle {..}).
    • Component: A Data object bound to hardware via IO, Reg, Wire, etc. (e.g., Wire(UInt(3.W)) is a component of type UInt(3.W)).
    • Aggregate: A type or component containing other types/components (e.g., Vec, Record, Bundle).
    • Element: A type or component that does not contain others (e.g., UInt, SInt, Bool).
    • Member: Any Chisel type/component or its children (e.g., p.alignedChild is a member of p).
    • Structural type check: Determines if two types are equivalent based on field names, types, probe modifiers, and vector sizes, ignoring relative alignment.
    • Alignment type check: Determines if two types match alignment by checking if corresponding members have the same relative alignment (aligned vs flipped) within their respective parents.

  5. Understand the purpose of Annotations in Chisel

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    In Chisel, Annotations are metadata containers associated with elements in a FIRRTL circuit. They act as arguments for specific FIRRTL Transforms, allowing Chisel to communicate information (such as optimization constraints) to the downstream FIRRTL compiler.

    Note: Annotations are intended to be implementation details. Users should not manually construct or interact with them directly. Instead, use high-level Chisel APIs that wrap these annotations. For example, the dontTouch API is used to prevent a wire or port from being optimized; this API internally manages a DontTouchAnnotation so the user doesn't have to.

  6. Chisel Local Setup Requirements

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    To run Chisel locally, you need the following core components:

    • SBT (Scala Build Tool): The minimal requirement. SBT automatically fetches the appropriate Scala and Chisel versions based on your project configuration.
    • Firtool: Required to generate Verilog from Chisel.
    • Verilator: Required to simulate your Verilog designs.
    • FileCheck: Used by many of the Chisel unit tests to match output text (look for CHECK: in tests).

  7. Explore Chisel learning resources

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    Chisel provides several paths for learning depending on your needs:

    • Cookbooks: Quick reference "How-To" guides for common tasks.
    • Digital Design with Chisel: A textbook for learning both Chisel and general digital design principles.
    • Explanations: Deep dives into key Chisel concepts.
    • API Documentation: Detailed technical reference for the Chisel source code.
    • Resources: Links to external tools and learning materials.

  8. Understand Chisel Architecture and Sub-projects

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    The Chisel compiler is composed of several layers:

    • Frontend (chisel3.*): The public API used for writing RTL.
    • Builder (chisel3.internal.Builder): Maintains global state (like the current Module) and generates intermediate structures.
    • Intermediate Data Structures (chisel3.firrtl.*): Syntactically similar to Firrtl; represents the elaborated circuit.
    • Firrtl Emitter (chisel3.firrtl.Emitter): Converts intermediate structures into Firrtl files.
    • Standard Library (chisel3.util.*): Contains circuit generators like Decoupled, arbiters, and multiplexors.
    • Chisel Stage (chisel3.stage.*): Contains compilation and test functions for Verilog generation and simulation.

    Sub-projects:

    • core: The bulk of the source code; depends on firrtl, svsim, and macros.
    • firrtl: Vestigial remains of the old Scala FIRRTL compiler.
    • macros: Macros used in Chisel.
    • plugin: The Scalac compiler plugin.
    • src/main: The main entry point including the util library.
    • svsim: Low-level library for controlling SystemVerilog simulations (Verilator/VCS).

  9. Understand Chisel Properties

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    Chisel properties allow you to capture non-hardware information (domain-specific knowledge and design intent) alongside your hardware description. Unlike standard Chisel Data Types, properties do not flow through or affect the generated hardware circuits. Instead, they flow through the design hierarchy as ports that can be connected, allowing you to build data models that are tightly coupled to your hardware hierarchy.

  10. Understand Chisel Data Types

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    Chisel uses specific types to represent hardware values, which are distinct from Scala's built-in types.

    Key types include:

    • Bits: A raw collection of bits.
    • UInt: Unsigned integers.
    • SInt: Signed integers (using two's-complement format).
    • Bool: Boolean values.
    • Bundle: A collection of values with named fields (similar to a struct).
    • Vec: An indexable collection of values.

  11. Explore Chisel and FIRRTL projects

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    The Chisel community includes a wide range of hardware generators, accelerators, and research tools. Notable projects include:

    Chisel Projects

    • Rocket Chip Generator: RISC-V System-on-Chip Generator.
    • Berkeley Out-of-order Machine (BOOM): RISC-V Out-of-order/Multi-issue Microprocessor.
    • Gemmini: Systolic-array Accelerator Generator.
    • Edge TPU: AI Inference Accelerator.
    • RISCVAssembler: A RISC-V assembler library for Scala/Chisel projects.

    Tooling

    • Tywaves: A type-based waveform viewer for Chisel.

    FIRRTL Projects

    • MIDAS/DESSERT/Golden Gate: FPGA Accelerated Simulation.
    • Chiffre: Run-time Fault Injection.
    • SIRRTL: Security-typed FIRRTL.
    • obfuscation: Transforms to obfuscate FIRRTL circuits.
    • Area/Timing Estimates: Transforms for area and timing estimates.

  12. Understand Chisel Project Versioning

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    Chisel follows Semantic Versioning 2.0.0 (MAJOR.MINOR.PATCH).

    • MAJOR: Incremented for backwards incompatible changes (following a deprecation schedule).
    • MINOR: Incremented for new, backwards compatible functionality. Chisel maintains binary compatibility between minor versions of the same major version (e.g., code compiled against Chisel 5.0.0 is compatible with Chisel 5.1.0).
    • PATCH: Incremented for backwards compatible bug fixes.