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Analog Devices, Inc. HDL Libraries and Reference Designs

repository·main·Indexed 24 days ago

https://github.com/analogdevicesinc/hdl

HDL libraries and reference designs (Verilog/VHDL) for FPGA prototyping systems, including source code and Tcl scripts for AMD Xilinx and Intel toolchains. Features include the AXI Clock Monitor, Corundum IP Core, and specific projects for RF data converters and DACs such as AD-QUADMXFE1-EBZ (supporting AD9081 and AD9082), AD353XR, AD35XXR-EVB, and AD4052-ARDZ across various carrier boards like VCU118, ZED, CORAZ7S, and DE10-Nano.

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What's inside analogdevicesinc-hdl

  2. Overview of the CN0363 HDL Project

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    The CN0363 HDL project provides hardware description language (HDL) support for the CN0363 evaluation board. The system is a dual-channel RGB colorimeter featuring a programmable gain TIA, digital synchronous detection, and a high-sensitivity, low-noise transimpedance amplifier.

    Key resources:

  3. Overview of the CN0579 HDL Project

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    The CN0579 HDL project provides hardware description language (HDL) implementations for the CN0579 evaluation board. This project supports high-precision data acquisition using specific Analog Devices components.

    Key Resources:

    Hardware Specifications:

    • Evaluation board VIO: 3.3V

  4. Overview of the ADAQ7980-SDZ HDL Project

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    The ADAQ7980-SDZ HDL project provides hardware description language (HDL) implementations for the ADAQ7980 and ADAQ7988 integrated data acquisition subsystems. This project is designed for use with the EVAL-ADAQ7980 evaluation board.

    Key Resources:

    Hardware Note:

    • The evaluation board VADJ is 3.3V.

  5. Overview of AXI AD9783 IP Core

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    The AXI AD9783 IP core provides an interface for the AD9783 dual DAC device. The AD9783 is a 16-bit resolution dual DAC that interfaces via LVDS and supports sample rates up to 500 MSPS.

    Key Features:

    • AXI Memory-Mapped to Streaming control/status interface.
    • PRBS monitoring and Internal DDS.
    • BIST (Built-In Self-Test) testing.
    • Note: This core supports Xilinx devices only.

  6. Overview of AXI AD777x IP Core

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    The AXI AD777x IP core is designed to interface with AD7770, AD7771, and AD7779 converters. It supports using 1, 2, or 4 active data lines.

    Key Features:

    • AXI-based configuration via a standard AXI Slave Memory Map interface (s_axi).
    • CRC validation flag for data integrity.
    • Configurable number of active data lines.
    • Real-time data header access.
    • Compatibility with both Vivado and Quartus design environments.

  7. Overview of the AD9209-FMCA-EBZ HDL Project

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    The AD9209-FMCA-EBZ HDL project is designed for evaluating the AD9209 (the RX side) of the system.

    Key resources:

    Supported Parts:

    • AD9209: 12-Bit, 4GSPS, JESD204B/C, Quad Analog-to-Digital Converter

  8. Overview of the AD9656-FMC HDL Project

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    The AD9656-FMC HDL project provides hardware description language (HDL) support for the AD9656, a 16-bit, 2Quad, 125 MSPS JESD204B 1.8 V Analog-to-Digital Converter. This project is designed for use with the EVAL-AD9656 evaluation board.

    Key Resources

    Hardware Specifications

    • VADJ Range: 1.2V - 2.5V

  9. Overview of the AD9213-EVB HDL Project

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    The AD9213-EVB HDL project provides hardware description language (HDL) support for the AD9213 evaluation board. This project is designed for the AD9213, a 12-Bit, 10.25 GSPS, JESD204B, RF Analog-to-Digital Converter.

    Key Specifications:

    • Evaluation Board VADJ: 1.8V
    • Supported Part: AD9213

    Resources:

  10. Overview of the AD9081-FMCA-EBZ-X-BAND HDL Project

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    The AD9081-FMCA-EBZ-X-BAND HDL project provides hardware description language support for the X-Band Phased Array Platform and related evaluation boards. It is designed to work with the AD9081 MxFE (Quad 16-Bit 12 GSPS RF DAC and Quad 12-Bit 4 GSPS RF ADC).

    Key Resources:

    Hardware Specifications:

    • VADJ Range: 1.2V - 3.3V (applies to the XUD custom breakout board; PMODs operate at 3.3V).

  11. Overview of AXI ADAQ8092 IP Core

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    The AXI ADAQ8092 IP core provides an interface for the ADAQ8092 ADC. It supports multiple data modes including DDR, LVDS/CMOS, or SDR CMOS.

    Key features include:

    • AXI-based configuration via a standard AXI Slave Memory Map interface.
    • DC filtering and configurable line delays.
    • Support for digital output randomize output mode decoding and alternate bit polarity output mode decoding.
    • Vivado compatibility.

  12. Overview of the ADMX6020M HDL Project

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    The ADMX6020M HDL project provides hardware description language files for the ADMX6020M evaluation board. This project supports the HMCAD1520 High Speed Multi-Mode A/D Converter.

    Key Specifications:

    • Supported Part: HMCAD1520 (High Speed Multi-Mode 8/12/14-Bit 1000/640/105 MSPS A/D Converter)
    • Evaluation Board VADJ: 2.5V

    For detailed technical information, refer to the HDL project documentation.